Alignment Mark Pillars for 3D NAND Tier Joining
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Solution Overview
Problem
In three-dimensionally stacked NAND-type flash memory devices, achieving precise alignment of memory cell pillars during manufacturing is challenging, especially when using cross-point processing, as it complicates the formation of alignment marks and can lead to difficulties in joining upper and lower tiers effectively.
Innovation Solution
The semiconductor device employs a configuration with alternating insulating and conductive layers, including alignment mark pillars that project from the stacked structure, allowing for clear alignment marks surrounded by these pillars, facilitating the formation of memory pillars and ensuring accurate alignment during the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If cross-point processing is used to form memory cell pillars, then three-dimensional stacking is achieved, but alignment mark formation becomes complicated and manufacturing precision deteriorates
Solution Approach 1:
The patent divides the stacked structure into multiple segments by introducing dividing structures that partition the conductive layers. This segmentation allows alignment marks to be formed in distinct regions, simplifying the alignment process while maintaining three-dimensional stacking. The dividing structures create separate zones where alignment marks can be clearly defined without interference from cross-point processing complexity.
Solution Approach 2:
The patent introduces alignment mark pillars as intermediary structures that facilitate precise alignment between tiers. These pillars project from the stacked structure and serve as reference points for alignment, mediating the alignment process between the complex cross-point processed memory cell pillars and the manufacturing equipment, thereby improving alignment precision without compromising the three-dimensional stacking architecture.
2Manufacturing precision
If alignment marks are formed in cross-point processed structures, then tier alignment is attempted, but the complexity of the structure makes clear alignment mark definition difficult
Solution Approach 1:
The patent extracts alignment mark formation from the complex cross-point processed structure by creating separate alignment mark pillars that project from the stacked structure. This extraction allows alignment marks to be defined independently from the memory cell pillar formation process, reducing the complexity of alignment mark definition while maintaining precise tier alignment capability.
Solution Approach 2:
The patent adds a vertical dimension to alignment mark definition by having alignment mark pillars project from the stacked structure in the thickness direction. This dimensional change allows alignment marks to be clearly defined in three-dimensional space, overcoming the planar limitation of cross-point processed structures and enabling precise tier alignment without increasing in-plane structural complexity.
3Productivity
If multiple tiers are joined directly without intermediate structures, then manufacturing steps are reduced, but alignment accuracy between tiers deteriorates
Solution Approach 1:
The patent performs preliminary alignment by forming alignment mark pillars that project from the stacked structure before final tier joining. This preliminary action establishes precise alignment references in advance, ensuring accurate tier alignment while maintaining an efficient manufacturing process with minimal steps. The alignment mark pillars are prepared beforehand to guide the joining process.
Solution Approach 2:
The alignment mark pillars serve as intermediary structures that facilitate accurate tier joining without adding excessive manufacturing complexity. These pillars provide physical reference points that mediate the alignment between tiers during the joining process, ensuring high alignment accuracy while keeping the manufacturing process streamlined and efficient.
Data Source
AI summary
According to one embodiment, a semiconductor device comprising: a first stacked structure in which first insulating layers and first conductive layers are alternately stacked; a second stacked structure in which second insulating layers and second conductive layers are alternately stacked; a first memory pillar provided in the first stacked structure; a first dividing structure dividing the first conductive layers; a second memory pillar provided within the second stacked structure and connected to the first memory pillar; a second dividing structure dividing the second conductive layers; a first alignment mark pillar provided in the first stacked structure and projecting from the first stacked structure; a second alignment mark pillar provided on the first alignment mark pillar; an alignment mark surrounded by the second alignment mark pillar.