Semiconductor Alignment Mark Placement for Rotational Bias Reduction
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Solution Overview
Problem
Advanced wafer-level packaging technology faces alignment biases during the fabrication of redistribution structures, leading to misplacement and displacement of devices, resulting in undesirable displacement of fabricated patterns due to rotational biases.
Innovation Solution
Forming alignment marks adjacent to the geometric center of semiconductor devices, allowing for precise alignment of masks during exposure processes and reducing the impact of rotational biases, thereby enhancing dimensional precision in pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If alignment marks are positioned off-center on alignment dies during wafer-level packaging, then the fabrication process can be simplified, but rotational bias occurs causing significant displacement of fabricated patterns
Solution Approach 1:
The patent positions alignment marks at the geometric center of alignment dies, creating a symmetric configuration that eliminates rotational bias. This central positioning ensures that any rotational displacement during handling affects all alignment marks equally, maintaining their relative positions and enabling accurate pattern fabrication without the +/−10 μm displacement caused by off-center mark placement
2Productivity
If multiple devices are processed together on a carrier in wafer-level packaging, then manufacturing time and cost are reduced, but devices may be misplaced or displaced during fabrication causing alignment bias
Solution Approach 1:
The patent introduces a carrier as an intermediary platform that provides precise positioning features and mechanical constraints for holding multiple alignment dies and chips. The carrier's design includes positioning mechanisms that maintain the geometric center alignment of each device, preventing misplacement during handling while enabling batch processing of multiple devices simultaneously
3Adaptability or versatility
If alignment marks are positioned away from the geometric center to accommodate other structures, then device design flexibility increases, but the relative position between alignment marks becomes highly sensitive to rotational bias
Solution Approach 1:
The patent positions alignment marks at the geometric center of alignment dies, creating a symmetric configuration that eliminates rotational bias. This central positioning ensures that any rotational displacement during handling affects all alignment marks equally, maintaining their relative positions and enabling accurate pattern fabrication without the +/−10 μm displacement caused by off-center mark placement
Data Source
AI summary
A semiconductor device package includes a semiconductor device, a sealant, a first dielectric layer, an electrically conductive layer, and a second dielectric layer. The semiconductor device includes a contact pad, an active surface, and side surfaces, where the contact pad is disposed adjacent to the active surface. The semiconductor device is formed with a first alignment mark that is disposed adjacent to the active surface. The sealant envelopes the side surfaces of the semiconductor device and exposes the contact pad. The first dielectric layer is disposed adjacent to the sealant and the active surface, and defines a first aperture that exposes the contact pad. The electrically conductive layer is disposed adjacent to the first dielectric layer and is electrically connected to the contact pad through the first aperture. The second dielectric layer is disposed adjacent to the electrically conductive layer.