Semiconductor Alignment Mark Planarization During CMP

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Solution Overview

Problem

The chemical mechanical polishing (CMP) process in semiconductor manufacturing leads to inaccuracies in alignment marks due to surface curvature and dishing defects, affecting device controllability and substrate area efficiency.

Innovation Solution

A method involving the use of a CMP stop layer, trench formation, metal layer deposition, and a sacrificial organic layer followed by CMP and ashing processes to create planar alignment marks, ensuring uniform planarization and accurate alignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Shape

If CMP process is used for planarization, then substrate surface flatness is improved, but alignment mark accuracy deteriorates due to surface curvature and dishing defects

Engineering Contradiction:

Improvesubstrate surface flatnessVSAvoidalignment mark accuracy

Core Design Contradiction:

ShapeVSManufacturing precision

Solution Approach 1:

The substrate surface is divided into two functional zones: a planarization region for general flatness and an alignment mark region for precise positioning. The CMP process selectively planarizes only the region where alignment marks are formed, while leaving other areas untouched. This segmentation allows simultaneous achievement of surface flatness and alignment mark accuracy by applying different treatments to different regions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention applies local quality by providing the alignment mark region with specialized properties distinct from the rest of the substrate. The alignment mark region undergoes controlled CMP processing to achieve optimal flatness without the dishing defects that affect overall substrate planarization. This localized treatment ensures high precision for alignment marks while maintaining overall device functionality.

Inventive Principle:

Principle #3Local quality

2Area of moving object

If CMP process is used for planarization, then device density is improved, but device controllability deteriorates due to alignment inaccuracies

Engineering Contradiction:

Improvesubstrate surface area utilizationVSAvoiddevice controllability

Core Design Contradiction:

Area of moving objectVSReliability

Solution Approach 1:

The substrate is segmented into functional regions with different requirements. The alignment mark region receives dedicated CMP treatment to ensure precise positioning, while other regions maintain their original characteristics for device operation. This segmentation enables high device density through efficient space utilization while preserving device controllability through accurate alignment marks.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The CMP process is applied preliminarily to the alignment mark region before device fabrication to establish precise positional references. By pre-planarizing the alignment mark region, the invention ensures accurate positioning of subsequent device structures, thereby maintaining device controllability even as device density increases.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If CMP process is used for planarization, then manufacturing efficiency is improved, but alignment mark quality deteriorates due to abrasive particle residue

Engineering Contradiction:

Improvemanufacturing efficiencyVSAvoidalignment mark quality

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The CMP process is segmented to treat only the alignment mark region, reducing overall processing time and abrasive particle accumulation. By limiting CMP application to specific areas rather than the entire substrate, the invention maintains manufacturing efficiency while minimizing abrasive residue that could compromise alignment mark quality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention extracts the CMP process from being a universal planarization step and applies it only where needed - specifically to the alignment mark region. This extraction eliminates unnecessary CMP processing in other areas, reducing abrasive particle residue and improving alignment mark quality while preserving manufacturing efficiency through selective application.

Inventive Principle:

Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances device fabrication accuracy by preventing dishing and curving of metallic layers, improving alignment mark quality and reducing abrasive particle residue, thus enhancing device controllability and substrate area utilization.

Implementation Method 1

chemical mechanical polishing (CMP)

Methodology Applied

Scientific EffectChemical mechanical polishing:

Implementation Method 2

ashing is performed to remove a remaining portion of the organic layer

Methodology Applied

Scientific EffectAashing:

Data Source

PatentUS12456649B2Semiconductor device and methods of manufacturing thereof

Publication Date: 2025.10.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.