Alignment Mark Protection Pattern for Semiconductor Chip
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Solution Overview
Problem
During semiconductor package manufacturing, alignment mark contamination occurs due to height differences between alignment marks and insulating patterns, leading to recognition errors during chip alignment on the package substrate, which affects the accuracy of seating semiconductor chips at predetermined positions.
Innovation Solution
An alignment mark protection pattern, typically made of metal material, is disposed on the alignment mark pattern to offset height differences and prevent contamination by covering the alignment mark, ensuring the surface remains clean and recognizable during the packaging process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If alignment mark pattern is disposed on the chip surface, then alignment accuracy is improved, but the alignment mark is susceptible to contamination from surrounding structures
Solution Approach 1:
A protection pattern is introduced as an intermediary element between the alignment mark pattern and the surrounding insulating patterns. This protection pattern acts as a barrier that prevents harmful factors (contamination) from reaching the alignment mark, while allowing the alignment mark to maintain its function for accurate alignment.
Solution Approach 2:
The protection pattern is formed in advance before the alignment inspection process. By pre-establishing this protective structure, the alignment mark is shielded from potential contamination during subsequent packaging processes, ensuring clean and accurate alignment mark images during inspection.
2Reliability
If insulating patterns are formed around redistribution layer, then electrical insulation is improved, but height differences cause alignment mark contamination
Solution Approach 1:
The protection pattern serves as a mediator between the insulating patterns and the alignment mark pattern. It prevents the insulating patterns from directly contacting or contaminating the alignment mark, thereby maintaining both electrical insulation functionality and alignment mark cleanliness.
Solution Approach 2:
The structure is segmented into distinct functional zones: the alignment mark pattern for alignment, the insulating patterns for electrical isolation, and the protection pattern as a buffer zone between them. This segmentation allows each element to perform its function without interfering with or contaminating the others.
3Ease of operation
If alignment mark is exposed on chip surface, then alignment inspection is simplified, but contamination from manufacturing processes reduces inspection accuracy
Solution Approach 1:
The protection pattern is formed in advance to shield the alignment mark before any contamination-prone manufacturing steps occur. This preliminary protective measure ensures that the alignment mark remains clean and accessible for inspection without requiring complex contamination control measures during subsequent processes.
Solution Approach 2:
The protection pattern acts as an intermediary layer that allows the alignment mark to remain functionally exposed for inspection while physically protecting it from contamination. The alignment inspection device can still access the alignment mark through or over the protection pattern, maintaining simplicity while improving accuracy.
Data Source
AI summary
A semiconductor chip includes a chip body, a redistribution layer pattern disposed on a surface of the chip body, an alignment mark pattern disposed to be spaced apart from the redistribution layer pattern on the surface of the chip body, a first insulating pattern disposed to contact a side surface of the redistribution layer pattern and a side surface of the alignment mark pattern on the surface of the chip body, a second insulating pattern disposed on the redistribution layer pattern to protect the redistribution layer pattern, and an alignment mark protection pattern disposed on the alignment mark pattern.