Alignment Mark Protection in Semiconductor Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
During the planarizing process in semiconductor device fabrication, alignment marks are often damaged, leading to defects that can be transferred to the substrate, which affects the accuracy and reliability of the superjunction power device.
Innovation Solution
A method involving the formation of a stopper layer and alignment mark material in the scribe lane region, where the stopper layer protects the alignment mark by being conformally deposited and planarized up to the substrate's surface, preventing damage during the planarizing process and ensuring no defects are transferred to the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a planarizing process is performed to form deep trenches and epitaxial layers, then manufacturing precision is improved, but alignment marks are damaged leading to defects
Solution Approach 1:
The alignment mark is formed before the planarizing process, and a protective layer is deposited over it in advance. This preliminary action ensures the alignment mark is in place for subsequent processing while being protected from damage during planarization.
Solution Approach 2:
A protective layer is introduced as an intermediary element between the alignment mark and the planarizing process. This protective layer absorbs the mechanical stress and prevents direct contact between the planarization tools and the alignment mark, thereby preventing damage.
2Manufacturing precision
If alignment marks are used for accurate alignment during layer to layer matching, then manufacturing precision is improved, but the alignment marks are damaged by the planarizing process
Solution Approach 1:
The protective layer serves as an intermediary that shields the alignment mark from the harmful mechanical effects of the planarizing process. This layer is specifically designed to withstand planarization conditions while preserving the underlying alignment mark structure.
Solution Approach 2:
The protective layer is deposited beforehand to cushion and absorb the mechanical stress that would otherwise be transmitted to the alignment mark during planarization. This prior cushioning prevents damage before it can occur.
3Manufacturing precision
If the planarizing process is performed to ensure proper layer formation, then manufacturing precision is improved, but defects are transited to the substrate
Solution Approach 1:
The protective layer acts as an intermediary barrier that prevents defect generation and transmission to the substrate during the planarizing process. By absorbing mechanical stress and preventing direct tool-substrate contact, it eliminates the harmful effects that would otherwise create defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents alignment mark damage and defect transfer, maintaining the integrity of the alignment marks and substrate, thereby enhancing the fabrication process's accuracy and reliability.
Implementation Method 1
A stopper layer is formed in a part in the trench
Data Source
AI summary
Provided is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device includes preparing a substrate in which a scribe lane region and a chip region are defined, forming a trench in the scribe lane region of the substrate, forming a stopper layer in a part in the trench, and forming an alignment mark material on the stopper layer.