Semiconductor Alignment Mark Recess Structure for Overlay Accuracy

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Solution Overview

Problem

The challenge in semiconductor manufacturing is the formation of alignment marks with insufficient visibility, which affects the accuracy of overlapping exposure steps, leading to potential misalignment issues.

Innovation Solution

A method involving the formation of a hydrophobic first film on a substrate, followed by treating its surface to be hydrophilic and polishing until the insulating film is exposed, enhances the visibility of alignment marks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If an alignment mark is formed using conventional methods, then the manufacturing process can proceed, but the visibility of the alignment mark is insufficient, leading to poor overlapping accuracy

Engineering Contradiction:
Improvealignment mark visibilityVSAvoidoverlapping accuracy
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating a recess portion at a specific location on the insulating film to enhance the alignment mark's visibility. The recess is formed only where needed (at the alignment mark position) rather than modifying the entire surface, thereby improving measurement precision without unnecessarily complicating the overall manufacturing process.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces a vertical dimension by forming a recess portion that extends downward from the upper surface of the insulating film. This creates a depth dimension (z-axis) in addition to the horizontal plane, allowing the alignment mark to have enhanced visibility through the recess structure while maintaining the original planar layout for other manufacturing purposes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If the visibility of alignment marks is improved through additional processing steps, then overlapping accuracy enhances, but the manufacturing process complexity increases

Engineering Contradiction:
Improveoverlapping accuracyVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the alignment mark formation process with the existing insulating film formation process. The recess portion is formed as part of the insulating film structure itself, combining two functions (insulation and alignment marking) into a single integrated structure, thereby improving overlapping accuracy without proportionally increasing process complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The insulating film serves multiple functions: it provides electrical insulation and simultaneously contains the recess portion that forms the alignment mark. This multi-functionality allows the same structural element to contribute to both electrical performance and alignment precision, reducing the need for separate dedicated alignment mark structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the visibility of alignment marks, ensuring precise alignment during exposure steps, thereby enhancing the manufacturing process's accuracy and reliability.

Implementation Method 1

forming a first film on the upper surface of the insulating film and along an inner surface of the recess portion, wherein the first film has hydrophobicity; treating an upper surface of the first film to be hydrophilic

Methodology Applied
Scientific EffectHydrophobicity to hydrophilic treatment: Wetting

Data Source

PatentUS20260082933A1Method of manufacturing semiconductor device and semiconductor device
Publication Date: 2026.03.19 KIOXIA CORP
  • US20260082933A1 patent drawing
  • US20260082933A1 patent drawing
  • US20260082933A1 patent drawing

AI summary

A method for manufacturing a semiconductor device includes forming an insulating film on a substrate; forming a recess portion extending toward the substrate from an upper surface of the insulating film; forming a first film on the upper surface of the insulating film and along an inner surface of the recess portion, wherein the first film has hydrophobicity; treating an upper surface of the first film to be hydrophilic; and polishing the first film until the upper surface of the insulating film is exposed.