Alignment Mark Refresh for DRAM Overlay Accuracy
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Solution Overview
Problem
Current methods for fabricating deep-trench capacitor DRAM devices fail to achieve satisfactory overlay accuracy for AA-DT and GC-DT, leading to defective or unreliable devices due to insufficient alignment precision.
Innovation Solution
A method involving a semiconductor substrate with a device region and an alignment-mark forming region, where a previous-layer alignment pattern with trench lines less than 0.5 micrometers is etched, and a 'k1 process is used to refresh the alignment pattern by etching away polysilicon, forming an overlay mark to assess and improve overlay accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional alignment marks and registration methods are used, then the fabrication process is simple, but the overlay accuracy for AA-DT and GC-DT is insufficient
Solution Approach 1:
The alignment mark is segmented into multiple components: a first alignment mark formed in the deep trench, a second alignment mark formed on the polysilicon layer, and a third alignment mark formed in the shallow trench. This segmentation allows for multi-stage alignment verification and correction, significantly improving overlay accuracy for AA-DT and GC-DT processes
Solution Approach 2:
The first alignment mark is formed in advance during the deep trench etching process, before polysilicon deposition. This preliminary alignment structure enables pre-verification of alignment accuracy, allowing corrections to be made before subsequent processing steps, thereby improving overall overlay precision
2Manufacturing precision
If the alignment pattern uses larger trench lines, then the etching process is easier, but the alignment precision deteriorates
Solution Approach 1:
Different regions of the alignment pattern have different trench line widths optimized for their specific functions. The first alignment mark in the deep trench uses narrower lines for higher precision, while the second alignment mark on the polysilicon layer uses wider lines for easier detection. This local optimization balances etching difficulty with alignment precision requirements
Solution Approach 2:
The alignment pattern utilizes multiple parameters including varying trench line widths (0.5-2.0 micrometers for deep trench, 1.0-3.0 micrometers for polysilicon layer), different depths, and varied spacing. These parameter variations enable both precise alignment measurement and manageable etching processes across different layers
3Manufacturing precision
If multiple alignment marks are formed, then the overlay accuracy assessment is improved, but the fabrication process complexity increases
Solution Approach 1:
Multiple alignment marks are integrated into the existing deep trench capacitor fabrication process flow. The first, second, and third alignment marks are formed during standard processing steps (trench etching, polysilicon deposition, shallow trench formation) without requiring separate dedicated alignment mark fabrication equipment or processes, thus maintaining productivity while improving overlay accuracy assessment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly enhances AA-DT and GC-DT overlay accuracy, improving the precision and reliability of deep-trench capacitor DRAM devices by using a small-size alignment pattern and the 'k1 process to refresh the trench profile.
Implementation Method 1
etching a capacitor trench into the semiconductor substrate within the device region, and simultaneously, etching a previous-layer alignment pattern into the semiconductor substrate within the alignment-mark forming region
Implementation Method 2
forming a trench capacitor structure within the capacitor trench comprising at least depositing polysilicon into the capacitor trench, wherein the polysilicon also deposits into the plurality of trench lines
Implementation Method 3
performing an exposure on the second photo resist layer using a photo mask bearing an active area pattern and transferring the active area pattern to the second photo resist layer
Data Source
AI summary
A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT and GC-DT overlay alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and to refresh the trench profile, thereby improving overlay alignment accuracy and precision.