Semiconductor Alignment Mark Topography via CMP Stop Layer
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Solution Overview
Problem
In semiconductor manufacturing, chemical mechanical polishing (CMP) processes struggle to effectively planarize surfaces with topography, leading to defocus issues during lithography and difficulty in detecting alignment marks due to flat surfaces, especially when covered by reflective material layers.
Innovation Solution
The method involves forming alignment marks with sufficient step height by creating trench openings and using CMP operations to stop on a CMP stop layer, followed by etch-back operations to maintain topography, allowing for strong alignment signals even under reflective metallic layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used to planarize the surface, then surface flatness is improved, but alignment mark detection capability deteriorates
Solution Approach 1:
The patent applies local quality by creating a recess structure specifically at the alignment mark location while maintaining planarization elsewhere. The CMP process is used to planarize the general surface, but a recess is intentionally created at the alignment mark position to preserve detection capability. This localized structural modification allows the alignment mark to maintain sufficient height difference for detection while the overall surface remains sufficiently flat for lithography.
2Ease of manufacture
If reflective material layer is deposited over alignment mark, then device structure is completed, but alignment signal strength deteriorates
Solution Approach 1:
The patent applies preliminary action by creating the recess structure at the alignment mark location before depositing the reflective material layer. By preparing the recess structure in advance, the alignment mark maintains sufficient height difference even after the reflective layer is deposited, ensuring that alignment signals remain detectable throughout the manufacturing process.
3Manufacturing precision
If complete planarization is performed, then lithography focus is improved, but topography for certain patterns is lost
Solution Approach 1:
The patent applies local quality by performing selective planarization that maintains different surface characteristics in different regions. The general surface is planarized to provide good lithography focus, while the alignment mark location maintains a recess structure to preserve necessary topography. This localized differentiation allows both requirements to be satisfied simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances alignment accuracy and maintains topography necessary for certain patterns, improving focus tolerance and signal strength during lithography operations.
Implementation Method 1
chemical mechanical polishing (CMP), performed on one or more layers formed by deposition
Implementation Method 2
followed by etch-back operations to maintain topography
Data Source
AI summary
In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a CMP stop layer is formed over the first ILD layer, a trench opening is formed by patterning the CMP stop layer and the first ILD layer, an underlying first process mark is formed by forming a first conductive layer in the trench opening, a lower dielectric layer is formed over the underlying first process mark, a middle dielectric layer is formed over the lower dielectric layer, an upper dielectric layer is formed over the middle dielectric layer, a planarization operation is performed on the upper, middle and lower dielectric layers so that a part of the middle dielectric layer remains over the underlying first process mark, and a second process mark by the lower dielectric layer is formed by removing the remaining part of the middle dielectric layer.