Alignment-Marker Data Streams for Low-Jitter Ethernet Synchronization

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Solution Overview

Problem

Existing Ethernet network data transmission solutions face complexity and high PLL jitter due to the implementation of Phase Locked Loop (PLL)-based clock and data recovery, which complicates clock extraction and synchronization processes.

Innovation Solution

A data processing method that involves first and second FEC encoding, followed by inserting alignment markers into data streams to simplify clock extraction and synchronization, ensuring the baud rate is an integer multiple of the Ethernet common reference clock frequency, thereby reducing PLL complexity and jitter.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If PLL-based clock and data recovery is implemented, then clock extraction and synchronization can be performed, but the implementation complexity increases and PLL jitter becomes high

Engineering Contradiction:
Improveclock extraction and synchronizationVSAvoidPLL circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Alignment markers are inserted into data streams before transmission, preparing the data in advance for easy synchronization. The markers are positioned at specific intervals (P bits from second data stream + W bits alignment marker) to enable the receiver to quickly acquire frame synchronization and inner codeword synchronization without complex PLL circuits

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Alignment markers serve as intermediary elements between the transmitter and receiver, providing clear synchronization points that facilitate clock extraction and data alignment. These markers act as reference signals that simplify the synchronization process, eliminating the need for complex PLL-based approaches

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If alignment markers are inserted into data streams, then frame synchronization and inner codeword synchronization are simplified, but the data stream structure becomes more complex

Engineering Contradiction:
Improvesynchronization operationVSAvoiddata stream structure
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The data stream is segmented into fixed-length frames, with each frame containing P bits from the second data stream followed by W bits of alignment marker. This segmentation creates regular, predictable structures that simplify synchronization operations at the receiver while maintaining manageable complexity through standardized framing

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250253866A1Data Processing Method and Data Processing Apparatus
Publication Date: 2025.08.07 HUAWEI TECH CO LTD
  • US20250253866A1 patent drawing
  • US20250253866A1 patent drawing
  • US20250253866A1 patent drawing

AI summary

This application discloses a data processing method. First data processing is performed on a plurality of first data streams obtained through first FEC encoding, to obtain m second data streams. Second FEC encoding has been performed for each of the second data streams, and each codeword obtained through the second FEC encoding includes N bits, where N=K+S. Second data processing is separately performed on the m second data streams to obtain m third data streams. Each of the third data streams includes at least one bit sequence, each bit sequence includes P+W bits, the P bits in each bit sequence are from the second data stream, and the W bits in each bit sequence are an added alignment marker, where P=N×b. Third data processing is performed on the m third data streams to obtain Y modulated symbol streams, where modulation has been performed for each of the modulated symbol streams.