Alignment Marker Search Circuitry With Fewer PCS Comparators
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Solution Overview
Problem
The challenge in high-speed Ethernet implementations, such as 40 GbE and 100 GbE, is the significant area usage and wire congestion caused by the large number of comparators required for alignment marker (AM) search in the physical coding sublayer (PCS), which complicates the layout process.
Innovation Solution
A two-stage AM search process is implemented, where an initial AM search is conducted on the read side of the PCS for all lanes, followed by sending the found AM value to the AM state machine on the write side, reducing the number of comparators needed from 400 to 40 for 100 GbE and from 16 to 8 for 40 GbE, thereby minimizing layout area usage and wire congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large number of comparators are used for alignment marker search in all lanes simultaneously, then the AM search coverage is complete, but the layout area usage increases significantly and wire congestion occurs
Solution Approach 1:
The AM search process is divided into two distinct stages: (1) an initial search stage that scans all lanes consecutively to find any AM, and (2) a verification stage that confirms the found AM across remaining lanes. This segmentation allows the system to use fewer comparators at any given time while still achieving complete AM detection coverage.
Solution Approach 2:
The initial AM search stage performs a preliminary scan of all lanes to identify potential AM locations before committing to a full verification process. This preliminary action reduces the search space for subsequent stages, allowing fewer comparators to be used in the verification phase while maintaining search completeness.
2Object-generated harmful factors
If comparators are reduced from 400 to 40 for 100 GbE and from 16 to 8 for 40 GbE, then wire congestion is alleviated, but the AM search process complexity increases
Solution Approach 1:
The search process is segmented into sequential phases with different comparator configurations. The initial phase uses a reduced set of comparators to perform a broad scan, then the system transitions to a verification phase with fewer comparators focused on specific lanes. This segmentation reduces peak comparator requirements and associated wire congestion while managing complexity through structured phase transitions.
Solution Approach 2:
The AM search operates in periodic cycles: an initial search phase followed by a verification phase, then resetting for the next potential AM occurrence. This periodic structure allows the system to reuse the same reduced set of comparators repeatedly, managing complexity through state machine control rather than requiring all comparators to operate simultaneously.
3Quantity of substance
If a two-stage AM search process is implemented, then the number of comparators is reduced, but the search time may increase due to sequential processing
Solution Approach 1:
The search is segmented into an initial phase that quickly scans all lanes using a subset of comparators, followed by a verification phase that confirms findings. The initial phase is designed to be fast by using consecutive lane scanning, while the verification phase is more targeted. This segmentation balances time and resource usage, reducing total comparator count while maintaining acceptable search timing.
Solution Approach 2:
The initial search stage performs a preliminary identification of AM candidates before the verification stage begins. This preliminary action filters out non-AM data early, reducing the workload for subsequent verification. The preliminary scan is optimized for speed with simple comparison logic, while verification uses more thorough checking with fewer comparators, overall reducing both time and resource requirements compared to full parallel verification.
Data Source
AI summary
Systems and methods for reducing a number of comparators used during an alignment marker (AM) search are presented. A method includes enabling communication between a physical coding sublayer (PCS) having a PCS transmit side and a PCS receive side with a physical medium attachment (PMA) sublayer, at a first end, using multiple PCS lanes that receives data blocks from the multiple PCS lanes, wherein a PCS lane includes an alignment marker (AM) on the PCS transmit side and performs an AM search using a first AM search stage circuit, wherein, in the first AM search stage circuit, all of the multiple PCS lanes are consecutively searched with read components on the PCS receive side until an AM is detected in all of the multiple PCS lanes.