Alignment Marks on Integrated Circuit Dies for Packaging Precision

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in reducing physical size and minimizing misalignment during the fabrication of integrated circuit dies, leading to potential damage and inefficiencies in packaging processes.

Innovation Solution

The formation of alignment marks on integrated circuit dies, which are electrically isolated from active and passive devices, helps in identifying the desired orientation and reducing undesired shifts or rotations during packaging, thereby enhancing the precision and reliability of die placement and assembly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If alignment marks are formed on integrated circuit dies, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvealignment precisionVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Alignment marks are formed during the semiconductor fabrication process before the dies are singulated and packaged. This preliminary formation of alignment marks allows them to be integrated into the manufacturing flow without requiring additional post-processing steps, thereby improving manufacturing precision while minimizing the increase in device complexity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The alignment marks are formed using existing conductive material layers and lithography patterns that are already part of the standard fabrication process. These marks serve their alignment function during packaging and can be removed or covered in subsequent packaging steps, effectively acting as temporary features that provide high precision without permanent complexity

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Reliability

If alignment marks are formed on integrated circuit dies, then reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvepackaging reliabilityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The alignment marks are formed using the same conductive material layers and lithography processes that are already used for creating functional circuit elements. This multi-functional approach allows the alignment marks to be created as a byproduct of existing manufacturing steps, improving packaging reliability without significantly increasing process complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The alignment marks are automatically detected and used by packaging equipment for precise die placement. The marks serve themselves as alignment references without requiring additional manual intervention or complex alignment procedures, thereby improving reliability while keeping the manufacturing process straightforward

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9685411B2Integrated circuit dies having alignment marks and methods of forming same
Publication Date: 2017.06.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9685411B2 patent drawing
  • US9685411B2 patent drawing
  • US9685411B2 patent drawing

AI summary

Dies having alignment marks and methods of forming the same are provided. A method includes forming a device on a substrate. A plurality of contact pads is formed over the substrate and the device. Simultaneously with forming the plurality of contact pads, one or more alignment marks are formed over the substrate and the device.