Alignment-Overlay Mark for Semiconductor Wafer Scribe Space Reduction
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Solution Overview
Problem
As the number of lithography steps increases for miniaturization of IC chips, the space for alignment marks and overlay marks on semiconductor wafers decreases, making it challenging to secure sufficient space for accurate alignment.
Innovation Solution
The use of an alignment-overlay mark that serves as both an alignment mark and an overlay mark, designed to occupy less scribe space on the wafer while maintaining alignment quality, by incorporating a pair of first marks and a plurality of second marks arranged in a grating pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate alignment marks and overlay marks are used, then alignment accuracy is maintained, but scribe space requirement increases
Solution Approach 1:
The patent combines separate alignment marks and overlay marks into a single integrated alignment-overlay mark structure. This mark includes a first mark for alignment purposes and a second mark for overlay purposes, both formed within the same scribe space. By merging these two previously separate mark types into one unified structure, the patent eliminates the need for additional scribe space while maintaining both alignment accuracy and overlay precision.
Solution Approach 2:
The alignment-overlay mark serves multiple functions simultaneously: the first mark provides alignment functionality while the second mark provides overlay functionality. This multi-functional design allows a single mark structure to perform the roles of two separate marks, thereby reducing the overall space requirement in the scribe area without compromising the precision of either alignment or overlay operations.
2Productivity
If scribe space is reduced to accommodate more IC chips, then chip density increases, but mark space becomes insufficient
Solution Approach 1:
By merging alignment marks and overlay marks into a single compact alignment-overlay mark structure, the patent reduces the total space required in each scribe. This consolidation enables more IC chips to be placed on the wafer with adequate mark space, thereby increasing chip density while maintaining the necessary alignment and overlay capabilities.
Solution Approach 2:
The patent utilizes the vertical dimension by forming the alignment-overlay mark in multiple layers or at different depths, allowing both the first mark (for alignment) and second mark (for overlay) to coexist in the same scribe footprint. This dimensional approach enables efficient space utilization and supports higher chip density without compromising mark functionality.
Data Source
AI summary
According to one or more embodiments of the disclosure, an alignment-overlay mark is provided. The alignment-overlay mark includes a pair of first marks and a plurality of second marks. The first marks extend in a first direction and are arranged in parallel to each other in a second direction. The second direction is perpendicular to the first direction. The second marks are between the first marks, extend in the second direction and are arranged in parallel to each other in the first direction.