Semiconductor Alignment Structure With Notched Dummy Gates
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in maintaining accurate alignment between components, particularly in FinFET devices, leading to issues such as footing features at the edges of alignment structures that can cause misalignment and reliability concerns.
Innovation Solution
The formation of alignment structures with dummy gates that include notches at the interfaces between the dummy gate stacks and STI regions, preventing footing features and improving alignment precision by using a multi-step etching process to shape the sacrificial gates, followed by the deposition of gate dielectric and electrode layers to form precise alignment marks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but alignment precision between components deteriorates
Solution Approach 1:
The patent introduces alignment structures as intermediary elements between the lithography system and the actual device features. These alignment structures include dummy gates with notches that serve as reference markers, enabling precise alignment measurements and corrections during the fabrication process, thereby maintaining alignment precision despite reduced feature sizes
Solution Approach 2:
The patent modifies the geometry of alignment structures by adding notches to dummy gates and adjusting their positions relative to STI regions. These parameter changes in the alignment structure design enable more accurate alignment reference points, compensating for the challenges posed by reduced minimum feature sizes
2Ease of manufacture
If alignment structures are formed without notches, then the manufacturing process is simpler, but footing features occur at edges causing misalignment
Solution Approach 1:
The patent applies local quality by adding notches only to specific locations (edges) of dummy gates where footing features are problematic, rather than redesigning the entire alignment structure. This localized modification prevents misalignment at critical edges while maintaining the overall simplicity of the manufacturing process
Data Source
AI summary
An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.