All-Around Gate Semiconductor Device with Strained Silicon Channel
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Solution Overview
Problem
Conventional semiconductor devices with vertical channels face challenges in increasing the mobility of electrons and holes, which is crucial for preventing the short channel effect and enhancing current supply capacity as device integration increases.
Innovation Solution
An all around gate type semiconductor device is developed with a vertical channel pillar made of silicon germanium (SiGe) and a surrounding silicon layer, where the SiGe pillar is doped with p-type or n-type impurities, and a gate electrode surrounds the silicon layer, along with source/drain contacts, to improve electron and hole mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the channel width is reduced to decrease device size, then the device integration increases, but the current supply capacity decreases due to shorter channel length
Solution Approach 1:
The patent transitions from planar channel structure to vertical channel structure, moving the channel conduction path from two-dimensional lateral flow to three-dimensional vertical flow. This dimensional change allows the channel to extend vertically through multiple layers (source region, channel region, drain region) stacked above the substrate, effectively increasing the channel length without increasing the lateral device footprint, thus maintaining current supply capacity while reducing device size.
Solution Approach 2:
The patent implements a nested structure where the channel region is surrounded by the gate electrode on all sides (top, bottom, and lateral surfaces), forming an all-around gate configuration. The gate electrode wraps around the channel like a nested structure, providing comprehensive control of the channel potential from multiple directions. This nested arrangement maximizes the gate's control efficiency over the vertical channel while minimizing the lateral space required.
2Device complexity
If conventional planar gate structure is used, then device structure is simple, but short channel effect occurs and mobility of electrons and holes decreases
Solution Approach 1:
The patent extends the gate structure from a planar two-dimensional configuration to a three-dimensional all-around configuration that wraps vertically and laterally around the channel. This dimensional extension allows the gate to control the channel from top, bottom, and lateral surfaces simultaneously, providing superior electrostatic control that prevents short channel effects while maintaining reasonable structural complexity through systematic layering.
Solution Approach 2:
The patent employs composite material structures including silicon germanium (SiGe) for the channel region, silicon oxide or silicon nitride for the gate oxide layer, and conductive materials for the gate electrode. These composite materials are strategically selected to optimize each functional layer: SiGe provides high carrier mobility, the gate oxide provides electrical isolation, and the conductive gate material provides low-resistance control, collectively enhancing device reliability.
3Reliability
If germanium content in SiGe pillar is increased to improve carrier mobility, then electron and hole mobility increases, but manufacturing precision becomes more difficult to control
Solution Approach 1:
The patent applies different germanium ratios at different vertical positions within the channel region. The SiGe channel layer has a first germanium ratio, while the SiGe contact layer has a second germanium ratio that differs from the first. This local variation in composition allows optimization of carrier mobility in the channel region while facilitating better contact properties at the contact region, and enables independent control of each layer's properties during manufacturing.
Solution Approach 2:
The patent divides the SiGe structure into multiple segmented layers with distinct functions and compositions: a SiGe channel layer with optimized germanium ratio for high carrier mobility, a SiGe contact layer with different germanium ratio for optimal electrical contact, and intermediate transition layers. This segmentation allows each layer to be independently optimized and manufactured with controlled germanium content, reducing the overall manufacturing difficulty compared to a uniform high-germanium structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases electron and hole mobility, thereby enhancing the current supply capacity and preventing the short channel effect, by utilizing a strained silicon layer over a SiGe pillar, which improves interface characteristics and carrier mobility.
Implementation Method 1
utilizing a strained silicon layer over a SiGe pillar, which improves interface characteristics and carrier mobility
Implementation Method 2
forming a SiGe layer in the pillar region by an epitaxy process using the silicon substrate as a seed. The epitaxy process is a vapor phase epitaxy process using chemical vapor of a silicon precursor and a germanium precursor
Data Source
AI summary
An all around gate type semiconductor device improves mobility of electrons and holes by using a silicon germanium pillar and a silicon layer surrounding the silicon germanium pillar as a vertical channel. A gate electrode is formed to surround the vertical channel. When a semiconductor device is used as a nMOSFET, the silicon layer strained by silicon germanium is used as the channel to increase electron mobility. When the semiconductor device is used as a pMOSFET, the silicon germanium pillar is used as the channel to increase hole mobility. Thus, the semiconductor device can enhance current supply capacity regardless of transistor type.