All-Around Junction-Gate JFET for Low-Voltage Current Control
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Solution Overview
Problem
There is a need for Junction Field Effect Transistors (JFETs) that operate with lower input voltage and low input power consumption, particularly for emerging mobile and IoT applications that require efficient and low-power hardware implementations for computationally intensive tasks.
Innovation Solution
A JFET design with multiple channels connected in parallel, where all-around gates are electrically connected to form p-n junctions, reducing the voltage required to control current flow and thus minimizing power consumption by creating multiple depletion regions with a single gate-source voltage connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional single junction gate devices are used, then device structure is simple, but voltage required to control current flow is high and power consumption is high
Solution Approach 1:
The patent divides the channel into multiple segments by introducing multiple gates (first gate and second gate) that contact different channel surfaces. Each gate creates independent depletion regions, allowing the channel to be controlled in segments. This segmentation enables lower voltage operation because each gate only needs to control a portion of the channel rather than the entire channel length, directly reducing power consumption while accepting increased structural complexity
Solution Approach 2:
The patent transitions from a conventional single-plane gate structure to a multi-dimensional gate arrangement where gates contact different surfaces of the channel (e.g., top surface and side surfaces). This dimensional expansion allows electric fields to be applied from multiple directions, creating more efficient depletion region formation that reduces the voltage required for channel control, thereby reducing power consumption at the cost of more complex device geometry
2Productivity
If multiple channels connected in parallel are used, then current flow increases and voltage control range is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple channel structures into a single integrated device architecture with parallel channels sharing common source and drain regions. The first and second gates are electrically connected to work together on the same channel, creating a unified control system. This merging approach increases current flow capacity through the parallel channels while consolidating control mechanisms, achieving higher productivity with managed complexity rather than proportionally increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the pinch-off voltage and the voltage range needed to control current flow, resulting in lower overall input power requirements, with the potential to halve the voltage needed compared to traditional single junction gate devices, while increasing current flow and reducing power consumption.
Implementation Method 1
A p-n junction (junction gate) is formed where one of the gates is in direct contact with one of the channel surfaces
Implementation Method 2
a voltage applied to the gates creates at least two depletion regions in each of the channels
Data Source
AI summary
A Junction Field Effect Transistor (JFET) has a source and a drain disposed on a substrate. The source and drain have an S/D doping with an S/D doping type. Two or more channels are electrically connected in parallel between the source and drain and can carry a current between the source and drain. Each of the channels has two or more channel surfaces. The channel has the same channel doping type as the S/D doping type. A first gate is in direct contact with one of the channel surfaces. One or more second gates is in direct contact with a respective second channel surface. The gates are doped with a gate doping that has a gate doping type opposite of the channel doping type. A p-n junction (junction gate) is formed where the gates and channel surfaces are in direct contact. The first and second gates are electrically connected so a voltage applied to the first and second gates creates at least two depletion regions in each of the channels. In some embodiments, the junction gates are formed all-around the channel surfaces. As a result, the current flowing in the channels between the source and drain can be controlled with less voltage applied to the gates and less power consumption.