All-Around Source/Drain Contacts for Nanosheet FETs
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Solution Overview
Problem
As semiconductor devices shrink, the increased resistance in source/drain regions due to reduced contact area between the upper surface of the source/drain epitaxy structure and the metal source/drain contact hinders performance.
Innovation Solution
The implementation of all-around source/drain contacts that encapsulate the source/drain epitaxy structures, increasing the contact area and reducing resistance by forming electrically conductive contacts around the nanosheets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional planar-type semiconductor devices are used, then the device footprint is larger, but the contact area between source/drain regions is sufficient
Solution Approach 1:
The patent transitions from planar contacts to three-dimensional all-around contacts that wrap around the nanosheet stack. The gate structure wraps around the nanosheet stack to define a channel region, and the source/drain contacts are formed on all surfaces of the nanosheet stack including top, bottom, and sidewalls. This dimensional transition increases contact area while reducing footprint by utilizing vertical and lateral surfaces rather than only planar surfaces.
Solution Approach 2:
The source/drain contacts are formed as nested structures that encapsulate the nanosheet stack. The first and second source/drain contacts are positioned to contact opposite sidewalls of the nanosheet stack, creating a nested configuration where contacts surround the channel region. This nesting approach maximizes contact area within a compact footprint.
2Area of stationary object
If device size is reduced to 7 nanometers and beyond, then the footprint is reduced, but the contact area between source/drain regions decreases leading to increased resistance
Solution Approach 1:
The patent addresses the contact resistance issue by transitioning to three-dimensional all-around contacts that contact the nanosheet stack on multiple surfaces including top, bottom, and sidewalls. This dimensional approach increases the effective contact area without increasing footprint, thereby maintaining low contact resistance in scaled devices.
Solution Approach 2:
The source/drain contacts are segmented into multiple contact regions distributed around the nanosheet stack. Rather than a single planar contact, the contacts are divided into multiple segments on different surfaces (top surface, bottom surface, sidewalls), which collectively provide sufficient total contact area to maintain low resistance while keeping the device footprint small.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the footprint of semiconductor devices while minimizing contact resistance in the source/drain regions, enhancing overall device performance.
Implementation Method 1
The gate structure is used to self-align the first and second sacrificial regions with respect to sidewalls of the nanosheet stack
Implementation Method 2
growing, from the first sacrificial region, a first source/drain epitaxy structure that contacts a first side of the nanosheet stack, and growing, from the second sacrificial region, a second source/drain epitaxy structure that contacts an opposing second side of the nanosheet stack
Implementation Method 3
replacing the first and second sacrificial regions and a portion of the first and second ILDs with an electrically conductive material to form an all-around source/drain contact that encapsulates the first and second source/drain epitaxy structures
Data Source
AI summary
A semiconductor device includes a semiconductor wafer having one or more suspended nanosheet extending between first and second source/drain regions. A gate structure wraps around the nanosheet stack to define a channel region located between the source/drain regions. The semiconductor device further includes a first all-around source/drain contact formed in the first source/drain region and a second all-around source/drain contact formed in the second source/drain region. The first and second all-around source/drain contacts each include a source/drain epitaxy structure and an electrically conductive external portion that encapsulates the source/drain epitaxy structure.


