All Bit Line Memory Sensing Architecture
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Solution Overview
Problem
Current flash memory devices require twice as long to read all bit lines due to the need to alternate between reading odd and even bit lines, resulting in bit line-to-bit line coupling and a recovery period before subsequent sense operations can occur.
Innovation Solution
Implementing an all bit line sense architecture that precharges and maintains bit lines at optimal voltage levels between sense operations, eliminating the need for grounding alternate bit lines and reducing coupling, allowing simultaneous sensing of all bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If alternate bit lines are read sequentially (odd then even), then bit line-to-bit line coupling is reduced, but read time is doubled
Solution Approach 1:
The patent precharges all bit lines to the same voltage level before the sense operation begins. This preliminary action ensures that when all bit lines are sensed simultaneously, there is no voltage differential between adjacent bit lines, thereby preventing bit line-to-bit line coupling while enabling parallel reading of all bit lines, thus resolving the contradiction between coupling reduction and read time reduction
Solution Approach 2:
Instead of the conventional approach of grounding non-selected bit lines to reduce coupling, this patent inverts the approach by precharging all bit lines to the same voltage level. This inversion eliminates the need for alternating read operations while maintaining coupling reduction, achieving both fast parallel reading and coupling mitigation
2Loss of time
If all bit lines are read simultaneously, then read time is reduced, but bit line-to-bit line coupling increases
Solution Approach 1:
The patent applies preliminary precharging to all bit lines before the simultaneous sense operation. This ensures that when all bit lines are active at the same time, they start from the same voltage potential, preventing coupling interference and enabling reliable parallel reading without the traditional penalty of increased coupling
Solution Approach 2:
The patent creates an equipotential condition across all bit lines by precharging them to the same voltage level. This equipotential state eliminates voltage differentials between adjacent bit lines during simultaneous sensing, thereby preventing coupling while enabling parallel operation, thus resolving the contradiction between read speed and coupling control
3Reliability
If bit lines are grounded between sense operations, then coupling is reduced, but recovery period is required
Solution Approach 1:
The patent maintains bit lines in a continuously precharged state throughout the sensing operation rather than grounding them between operations. This continuous useful action eliminates the need for recovery periods, as the bit lines remain ready for sensing without requiring voltage recovery, thereby removing the delay while maintaining coupling reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces read time by eliminating the recovery period between sense operations, enabling faster data retrieval without the need for alternating bit line reads.
Implementation Method 1
bit line precharge circuits coupled to the bit lines and configured to precharge the bit lines to different voltage levels based on the drain current of the selected memory cell
Implementation Method 2
sense circuitry (e.g., sense amplifiers) that detects the state of a target memory cell by sensing voltage or current on a particular bit line
Implementation Method 3
bit line clamp transistor configured to maintain the bit line voltage at an optimal voltage level during a sense operation
Data Source
AI summary
Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected.