All Levels Memory Programming via Level Shifting

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Solution Overview

Problem

Existing memory sub-systems face inefficiencies in programming multiple levels of memory cells, leading to longer programming times, higher energy consumption, and performance degradation due to sequential programming and high peak current levels.

Innovation Solution

Implementing an all levels programming operation where each programming pulse programs all levels simultaneously, involving a first phase with a ramping wordline voltage and floating pillars, followed by a second phase with a programming pulse applied to all levels, and iteratively repeating these phases until all levels are verified.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If sequential programming is used to program multiple levels of memory cells, then programming accuracy can be maintained, but programming time increases and productivity decreases

Engineering Contradiction:

Improveprogramming accuracyVSAvoidprogramming speed

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent merges the programming operations for multiple levels (e.g., SLC and TLC levels) into a single programming pulse operation. Instead of sequentially programming each level separately, the system applies one programming pulse that simultaneously programs all required levels, thereby maintaining accuracy while dramatically improving programming speed and productivity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary setup of voltage levels and pillar configurations before applying the programming pulse. By pre-configuring the memory device state (setting appropriate voltages on wordlines, bitlines, and pillars), the system ensures that a single programming pulse can accurately program multiple levels without requiring sequential verification and adjustment steps.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If multiple programming pulses are applied to program different levels, then programming completeness is achieved, but energy consumption increases

Engineering Contradiction:

Improveprogramming completenessVSAvoidenergy per bit

Core Design Contradiction:

Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The patent combines multiple programming operations into a single programming pulse that simultaneously programs multiple levels (SLC and TLC). This merging eliminates the need to apply separate programming pulses for each level, thereby achieving programming completeness while significantly reducing the total energy consumed per bit programmed.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The programming pulse is designed to serve multiple functions simultaneously: it programs both SLC and TLC levels, verifies both levels, and adjusts thresholds for both levels in a single operation. This multi-functionality reduces the total number of pulses required and thereby reduces overall energy consumption while ensuring complete programming of all levels.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Manufacturing precision

If sequential programming operations are performed, then programming accuracy is maintained, but peak current levels increase

Engineering Contradiction:

Improveprogramming accuracyVSAvoidpeak wordline current

Core Design Contradiction:

Manufacturing precisionVSStress or pressure

Solution Approach 1:

The patent merges programming operations for multiple levels into a single programming pulse, which distributes the current demand over time rather than concentrating it in sequential high-current pulses. This approach maintains programming accuracy through proper voltage level setup while reducing peak wordline current stress on the memory device.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The system performs preliminary voltage setup and pillar configuration before applying the programming pulse, ensuring that the programming pulse can be applied at optimized current levels. By pre-configuring the memory device state with appropriate voltages on control lines and pillars, the system achieves accurate programming without requiring excessive peak current during the actual programming operation.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250191659A1Level shifting in all levels programming of a memory device in a memory sub-system

Publication Date: 2025.06.12 MICRON TECHNOLOGY INC

AI summary

Control logic causes, during a program operation, a programming pulse to be applied to a memory cell of a set of memory cells to be programmed to a first programming level of a set of programming levels. The control logic further determines that a condition associated with the memory cell is satisfied. The control logic further executes a level shifting operation in response to the condition to be satisfied.