All-N-Type Gate Driver for Display Panels

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Solution Overview

Problem

The integration of P-type transistors in gate drivers for display panels complicates the manufacturing process and can lead to current leakage, resulting in flicker and degraded display quality.

Innovation Solution

A gate driver design that utilizes only N-type transistors, including an input circuit, pull-up circuit, pull-down circuit, QB node control circuit, and Q node control circuit, to simplify the manufacturing process and prevent current leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If P-type transistors are integrated in the gate driver, then the gate driver can be implemented with conventional transistor types, but the manufacturing process becomes complicated and current leakage occurs

Engineering Contradiction:
Improvecurrent leakage preventionVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies homogeneity by using only N-type transistors for all switching operations in the gate driver circuit. This uniform transistor type selection eliminates the need for mixed P-type and N-type transistor integration, simplifying the manufacturing process while preventing current leakage issues that arise from P-type transistor usage.

Inventive Principle:
Principle #33Homogeneity

2Reliability

If P-type transistors are used in the gate driver, then the circuit can function as designed, but current leakage causes flicker and deteriorates display quality

Engineering Contradiction:
Improvedisplay qualityVSAvoidcurrent leakage
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent uses exclusively N-type transistors throughout the gate driver circuit, creating a homogeneous transistor type system. This approach eliminates current leakage problems associated with P-type transistors, thereby preventing flicker and maintaining high display quality without requiring mixed transistor types.

Inventive Principle:
Principle #33Homogeneity

3Ease of manufacture

If only N-type transistors are used, then current leakage is prevented and manufacturing is simplified, but additional circuits are needed to achieve the same functionality

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidcircuit structure
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent employs parameter changes by modifying the voltage levels and signal characteristics to accommodate the all-N-type transistor architecture. By adjusting voltage parameters and signal timing, the circuit achieves the required functionality using only N-type transistors, simplifying manufacturing while managing the increased circuit complexity through parameter optimization.

Inventive Principle:
Principle #35Parameter changes

4Loss of energy

If all N-type transistors are used in the gate driver, then current leakage is eliminated and power consumption is reduced, but the circuit requires more components to achieve the same output

Engineering Contradiction:
Improvepower consumptionVSAvoidnumber of transistors
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent implements a homogeneous all-N-type transistor design that eliminates current leakage and reduces power consumption. While this approach requires additional transistor components compared to mixed-type designs, the power savings from eliminating leakage currents outweigh the increase in component count, achieving net energy efficiency improvement.

Inventive Principle:
Principle #33Homogeneity

Data Source

PatentUS20250124846A1Gate driver and display apparatus including the same
Publication Date: 2025.04.17 SAMSUNG DISPLAY CO LTD
  • US20250124846A1 patent drawing
  • US20250124846A1 patent drawing
  • US20250124846A1 patent drawing

AI summary

A gate driver includes an input circuit, a pull-up circuit, a pull-down circuit, a QB node control circuit and a Q node control circuit. The input circuit transmits an input signal to a Q node in response to a first clock signal. The pull-up circuit pulls up a gate output signal to a high voltage in response to a signal of a QF node. The pull-down circuit pulls down the gate output signal to a low voltage in response to a QB node. The QB node control circuit controls a signal of the QB node based on a QB control signal and a second clock signal. The Q node control circuit controls a signal of the Q node based on the QB node.