All-N-Type Gate Driver for Display Panels
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Solution Overview
Problem
The integration of P-type transistors in gate drivers for display panels complicates the manufacturing process and leads to current leakage, resulting in flicker and degraded display quality.
Innovation Solution
A gate driver design that utilizes only N-type transistors, including a pull-up circuit, multiple pull-down circuits, selection circuits, and a boosting circuit, to stabilize the output of gate signals and prevent current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If P-type transistors are integrated in the gate driver, then the gate driver can be implemented with conventional transistor types, but the manufacturing process becomes complicated and current leakage occurs
Solution Approach 1:
The patent extracts and removes P-type transistors from the gate driver circuit, implementing the entire gate driver using only N-type transistors. This extraction of the problematic P-type transistor component directly resolves the contradiction by simplifying the manufacturing process (removing the need for P-type transistor fabrication) while preventing current leakage (eliminating the source of leakage associated with P-type transistors in this application).
Solution Approach 2:
The patent changes the fundamental parameter of transistor type from mixed P-type and N-type to exclusively N-type. This parameter change transforms the gate driver architecture to use only N-type transistors with appropriately adjusted voltage levels and circuit configurations, thereby achieving both manufacturing simplification and leakage prevention.
2Reliability
If P-type transistors are used in the gate driver, then the circuit can function as designed, but current leakage causes flicker and deteriorates display quality
Solution Approach 1:
The patent converts the limitation of using only N-type transistors (which traditionally would require more complex voltage management) into a benefit by designing a circuit that eliminates current leakage entirely. The harmful effect of current leakage causing flicker is converted into a benefit of completely leakage-free operation, achieving stable gate signals and improved display quality.
Solution Approach 2:
By extracting and removing P-type transistors from the circuit, the patent eliminates the source of current leakage that causes flicker and display quality degradation. This extraction directly addresses the harmful factors while maintaining gate signal stability through the all-N-type transistor architecture.
3Reliability
If multiple pull-down circuits are added to the gate driver, then current leakage is prevented and signal stability is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of multiple pull-down circuits into a unified all-N-type transistor architecture. Instead of adding separate complex control mechanisms, the design integrates leakage prevention and signal stability functions into the fundamental transistor configuration itself, using the inherent characteristics of N-type transistors to achieve multiple functions simultaneously.
Solution Approach 2:
The all-N-type transistor design provides multi-functionality where the same transistor configuration simultaneously achieves current leakage prevention, signal stability, and simplified manufacturing. The universal N-type transistor architecture replaces what would otherwise require multiple specialized circuits, reducing overall device complexity while maintaining reliability.
Data Source
AI summary
A gate driver includes: a pull-up circuit configured to pull up a gate output signal to a high voltage in response to a signal at a first node of the pull-up circuit; a first pull-down circuit configured to pull down the gate output signal to a low voltage in response to a signal at a second node of the first pull-down circuit; a second pull-down circuit configured to pull down the gate output signal to the low voltage in response to a signal at a third node of the second pull-down circuit; a first selection circuit configured to activate the first pull-down circuit and deactivate the second pull-down circuit based on a first selection signal; and a second selection circuit configured to activate the second pull-down circuit and deactivate the first pull-down circuit based on a second selection signal.


