Alloyed Copper Interconnects for Electro-Migration Resistance
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Solution Overview
Problem
Copper interconnect structures in integrated circuits face reliability issues due to electro-migration, particularly at advanced technology nodes like 32 nm and below, where poor interfaces between copper and etch stop layers lead to void formation and increased RC delay, resulting in open circuits.
Innovation Solution
Incorporating alloying materials such as silicon and germanium in the seed layer and copper line, along with a pretreatment process using SiH4 and GeH4 gases, to form a dual-phase or ternary alloy interface region that enhances the resistance to electro-migration without significantly increasing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If pure copper is used in interconnect structures, then low resistivity is achieved, but electro-migration reliability deteriorates
Solution Approach 1:
The patent applies composite materials by creating an alloyed copper structure consisting of pure copper regions (for low resistivity) and alloyed copper regions containing silicon and germanium (for electro-migration resistance). This composite structure combines the beneficial properties of different material compositions to simultaneously achieve low resistivity and high reliability.
Solution Approach 2:
The patent implements local quality by creating spatially differentiated copper regions with different compositions. The pure copper is placed in regions where low resistivity is critical, while alloyed copper with silicon and germanium is placed at the interface with the etch stop layer where electro-migration resistance is critical. This local differentiation allows each region to optimize for its specific functional requirement.
2Reliability
If alloying materials are incorporated in copper interconnects, then electro-migration resistance is improved, but resistivity increases
Solution Approach 1:
The patent limits the alloying materials (silicon and germanium) to specific localized regions at the copper-etch stop layer interface, while maintaining pure copper in the bulk interconnect regions. This local quality approach ensures that electro-migration resistance is enhanced only where the interface vulnerability exists, without compromising the overall low resistivity of the copper interconnect structure.
Solution Approach 2:
The patent creates a composite copper structure where alloyed copper regions (providing electro-migration resistance) are combined with pure copper regions (providing low resistivity). The composite nature allows the structure to achieve both high reliability at the interface and low overall resistivity in the conductive paths.
3Ease of manufacture
If conventional lithographic and etching techniques are used, then manufacturing simplicity is maintained, but interface quality between copper and etch stop layer deteriorates
Solution Approach 1:
The patent applies preliminary action by incorporating alloying materials (silicon and germanium) into the copper structure before the final etch stop layer formation. The alloying process is performed in advance during copper deposition or subsequent thermal processing, preparing the copper interface to achieve better adhesion and electro-migration resistance before the etch stop layer is applied, thus maintaining manufacturing simplicity while improving interface quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach significantly improves the reliability of interconnect structures by increasing the time-dependent dielectric breakdown resistance, reducing the likelihood of delamination, and maintaining acceptable resistivity levels, as evidenced by a 20-fold increase in T50 values compared to pure copper structures.
Implementation Method 1
Incorporating alloying materials such as silicon and germanium in the seed layer and copper line, along with a pretreatment process using SiH4 and GeH4 gases, to form a dual-phase or ternary alloy interface region
Implementation Method 2
performing a pretreatment to a top surface of the copper line using a process gas selected from the group consisting essentially of SiH4 and GeH4
Data Source
AI summary
A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line.