Adaptive Logic Module 2LUT Architecture for Higher FPGA Packing Density
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Solution Overview
Problem
Programmable logic devices, such as FPGAs, face challenges in increasing logic density while minimizing power and die area consumption, as existing ALMs underutilize input and output pins, limiting function packing density and routability.
Innovation Solution
Implementing an additional two-input LUT (2LUT) in the ALM architecture to leverage unused inputs, improve small function packing density, and enhance routability, allowing for wider function mapping coverage with minimal impact on power and die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the quantity of ALMs is increased to enable more independent functions and wider functions, then logic density and performance are improved, but power consumption and die area increase
Solution Approach 1:
The additional 2LUT is designed to be universally applicable across multiple function types. It can operate independently as a separate logic function or be combined with the main 6LUT to create various composite functions. This multi-functionality allows the same hardware structure to serve different purposes, effectively increasing logic density without proportionally increasing die area.
Solution Approach 2:
The patent merges the additional 2LUT with the existing 6LUT structure by sharing input pins and combining logic functions. The 2LUT can be integrated with the 6LUT to create enhanced logic capabilities, such as implementing 7-input or 8-input functions by combining the output of the 6LUT with the 2LUT. This merging approach maximizes the utilization of available pins and reduces the overall die area required.
2Productivity
If the quantity of ALMs is increased to reduce critical path depth and improve data processing, then performance is improved, but power consumption increases
Solution Approach 1:
The additional 2LUT is merged with the existing 6LUT structure to create composite logic functions that reduce critical path depth. By combining the logic capabilities of both LUTs, the patent能够实现更复杂的逻辑功能在更少的层级中完成，从而减少关键路径深度，加快数据处理速度，同时避免简单增加ALM数量带来的功耗增加。
Solution Approach 2:
The additional 2LUT provides versatile logic capabilities that can be configured for different function types. This multi-functionality allows the ALM to implement a wider variety of logic functions with fewer ALMs, reducing the overall power consumption while maintaining or improving data processing speed.
3Device complexity
If existing ALM architecture is used with underutilized input and output pins, then device complexity is reduced, but function packing density and routability are limited
Solution Approach 1:
The additional 2LUT is designed with universal input and output pin sharing capabilities. It can share pins with the main 6LUT and be configured to implement various logic functions independently or in combination. This universality significantly increases function packing density without requiring additional dedicated pins, maintaining relatively simple device architecture while enhancing adaptability.
Solution Approach 2:
The patent segments the ALM into two independent but interoperable LUTs (6LUT and 2LUT), each capable of independent configuration and operation. This segmentation allows for greater flexibility in function packing, as each LUT can be independently programmed and combined with others. The segmented architecture also improves routability by providing additional independent logic units that can be strategically placed and connected.
Data Source
AI summary
To utilize unused or underused input and output pins without a large and undesirable impact on power and die area consumption, an adaptive logic module (ALM) of a programmable logic device may be implemented with an additional 2LUT to improve small function packing density and wide function mapping coverage. The 2LUT may also serve as a route-through to provide direct access to ALM registers with or without input inversion. The enhanced ALM may also use route-through configurations of the additional 2LUT to improve the connectivity of the ALM inputs and outputs.