ALM Transponder Clock Synchronization with DPLL Hold-Mode Correction
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Solution Overview
Problem
Existing solutions for in-frame synchronization between a reader carrier clock and an active load modulation (ALM) carrier clock in RFID systems are complex and increase costs, requiring sophisticated damping systems to manage phase drift and oscillations, which complicates the transponder design.
Innovation Solution
Implementing a digital phase locked loop (DPLL) that aligns the oscillator frequency with the reader carrier clock outside of transmission frames and occasionally corrects the phase of the ALM carrier clock within frames to maintain phase difference within a target range, allowing the DPLL to operate in hold mode and simplifying the damping system or eliminating it altogether.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a phase locked loop (PLL) with voltage controlled oscillator (VCO) is used to generate ALM carrier clock and put in hold mode during transmission, then the ALM transmission can take place with feedback opened, but frequency difference between ALM carrier clock and reader carrier clock causes phase drift above specified maximum
Solution Approach 1:
The patent implements dynamic switching between two operational modes of the PLL: lock mode for frequency synchronization and hold mode for transmission stability. The system dynamically adjusts the feedback loop state based on transmission phase requirements, allowing the VCO to maintain frequency while enabling controlled phase adjustments during gaps to prevent drift accumulation.
Solution Approach 2:
The patent employs periodic switching between lock mode and hold mode based on the transmission frame structure. During gaps between ALM carrier bursts, the system periodically re-locks the PLL to correct phase drift, while during active transmission periods, it switches to hold mode to maintain stability. This periodic mode switching aligns with the framed transmission protocol and prevents phase drift from exceeding specifications.
2Stability of the object's composition
If damping system is implemented to manage oscillations after ALM carrier bursts, then oscillation control is improved, but device complexity increases
Solution Approach 1:
The patent utilizes the PLL feedback mechanism to control oscillations rather than implementing separate damping hardware. The phase detector in the PLL continuously monitors phase differences and generates correction signals that naturally dampen oscillations. This feedback-based approach leverages existing circuitry to achieve oscillation control without adding dedicated damping components.
Solution Approach 2:
The PLL system serves dual functions: frequency synchronization and oscillation damping. The same feedback loop that maintains frequency lock also naturally suppresses signal oscillations after ALM carrier bursts. This self-service approach eliminates the need for separate damping systems, reducing device complexity while maintaining stability.
3Adaptability or versatility
If charge injection switch is used to put PLL in hold mode, then transmission mode switching is enabled, but charge injection changes voltage on VCO control pin causing frequency change
Solution Approach 1:
The patent prepares the VCO control voltage before switching to hold mode by gradually adjusting it to the target frequency level. This preliminary action ensures that when the switch transitions to hold mode, the VCO is already at the correct operating point, minimizing frequency disturbances. The control circuit pre-charges or pre-discharges the loop filter capacitor to the appropriate voltage level before mode switching occurs.
Solution Approach 2:
The patent implements cushioning measures by using a smooth transition circuit that prevents abrupt voltage changes on the VCO control pin during mode switching. The loop filter capacitor and associated circuitry are designed to absorb charge injection effects and provide a cushioned transition, preventing sudden frequency jumps when switching between lock and hold modes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the synchronization process, reduces complexity and cost, and maintains phase synchronization effectively without the need for precise oscillators or additional damping systems, enhancing the efficiency of wireless communication in challenging environments.
Implementation Method 1
synchronization between a reader carrier clock and an ALM carrier clock generated from a digital phase locked loop (DPLL) receiving said reader carrier clock
Implementation Method 2
correcting the phase of said ALM carrier clock at least one time in order to keep the variation of phase difference between said ALM carrier clock and said reader clock inside a target range
Implementation Method 3
using active load modulation (ALM) for transmitting information to the reader... the transponder generates the magnetic field which simulates load modulation of the reading device field performed by a passive transponder
Implementation Method 4
generates the magnetic field which simulates load modulation of the reading device field
Data Source
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AI summary
Transponder, configured to wireless communicate towards a reader using active load modulation, called ALM, comprising transmission means (14, 17) configured to transmit data frames to the reader through an antenna, synchronization means (16) comprising a digital phase locked loop adapted to receive a reader carrier clock (CKR) and to generate an ALM carrier clock (CKALM), first correction means (18) configured to correct the phase of said ALM carrier clock (CKALM) in order to keep the variation of phase difference between said ALM carrier clock (CKALM) and said reader carrier clock (CKR) inside a target range, and control means (15) configured to place outside of each transmitted frame, said digital phase locked loop in a lock mode in which the feedback loop is closed and to place within each transmitted frame said digital phase locked loop in an hold mode in which the feedback loop is opened and to activate said first correction means (18) at least one time within each transmitted frame.