Semiconductor-on-AlN Substrate Transfer via Barrier Oxide Splitting

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Solution Overview

Problem

The manufacture of silicon on aluminum nitride substrates using the bond and etch-back SOI approach is expensive, necessitating a more cost-effective method.

Innovation Solution

A method involving the formation of a first wafer structure with an aluminum nitride core substrate, followed by sequential deposition of dielectric and polysilicon layers, etching, and a barrier oxide layer, and a second wafer structure with a buffer and bonding layer, bonded at elevated temperatures and split using a thermal treatment process to create a semiconductor-on-insulator substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the bond and etch-back SOI approach is used to manufacture silicon on aluminum nitride substrates, then the semiconductor device characteristics are improved, but the manufacturing cost increases

Engineering Contradiction:
Improvesemiconductor device characteristicsVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The manufacturing process is divided into two separate wafer structures: a first wafer structure containing the aluminum nitride core substrate with barrier oxide layer, and a second wafer structure containing the semiconductor layers. These are bonded together and then separated, allowing independent optimization of each structure and reducing overall manufacturing complexity and cost.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A barrier oxide layer is introduced as an intermediary between the aluminum nitride core substrate and the semiconductor layers. This barrier layer facilitates the bonding process and enables the separation step, acting as a mediator that allows the cost-effective manufacturing approach while maintaining device performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the bond and etch-back SOI approach is used, then the parasitic capacitance and leakage current are reduced, but the manufacturing complexity increases

Engineering Contradiction:
Improveparasitic capacitance and leakage currentVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The process is segmented into distinct phases: forming the first wafer structure with barrier oxide, forming the second wafer structure with semiconductor layers, bonding them together, and separating them. This segmentation transforms a complex monolithic process into manageable discrete steps, reducing overall manufacturing complexity while achieving the desired device characteristics.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The barrier oxide layer is formed in advance on the aluminum nitride substrate before bonding, and the semiconductor layers are prepared separately on the second wafer structure. These preliminary actions prepare both structures for optimal bonding, simplifying the overall process by pre-configuring components rather than assembling them during the bonding step.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces manufacturing costs while maintaining improved semiconductor device characteristics, such as reduced parasitic capacitance and leakage current, and enables efficient growth of III-nitride materials.

Implementation Method 1

performing a hydrogen implanting process to implant hydrogen ions into the buffer layer to generate a splitting plane in the buffer layer

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

Performing a thermal treatment process to the buffer layer of the second wafer structure

Methodology Applied
Scientific EffectThermal treatment: Heat Treatment

Implementation Method 3

Performing a thermal treatment process to the buffer layer of the second wafer structure. Performing a splitting process to split the second wafer structure from the first wafer structure by inducing splitting at the splitting plane

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 4

Bonding the second wafer structure to the first wafer structure by performing a bond annealing process to join the capping layer to the barrier oxide layer

Methodology Applied
Scientific EffectDiffusion bonding: Diffusion Welding

Data Source

PatentUS20250372445A1Method of fabricating semiconductor substrate
Publication Date: 2025.12.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250372445A1 patent drawing
  • US20250372445A1 patent drawing
  • US20250372445A1 patent drawing

AI summary

A method of fabricating a semiconductor substrate includes the following steps. A first dielectric layer and a second dielectric layer are sequentially formed around an aluminum nitride core substrate. A polysilicon layer is formed on a front-side surface, a backside surface and side surfaces of the second dielectric layer. The polysilicon layer is removed from the front-side surface and the side surfaces, so that the polysilicon layer is retained on the backside surface of the second dielectric layer. A barrier oxide layer is formed around the aluminum nitride core substrate, the first and second dielectric layers, and the polysilicon layer. A wafer structure having a splitting plane is bonded onto the barrier oxide layer. A thermal treatment process is performed to mechanically split the wafer structure along the splitting plane into a first portion and a second portion, wherein the first portion is joined to the barrier oxide layer.