Normally-off III-nitride FET with AlN Gate Insulator
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Solution Overview
Problem
The incompatibility between the process of forming MOCVD AlN gate insulators and PECVD SiN passivation dielectrics in III-nitride transistors leads to degradation and processing compatibility issues, hindering the achievement of low leakage current and high breakdown voltage with low on-resistance in normally-off III-nitride transistors.
Innovation Solution
A method is developed to fabricate a normally-off III-nitride FET with a gate insulator stack comprising single-crystalline AlN, polycrystalline AlN, and SiN, where the single-crystalline AlN provides a high-quality interface and energy barrier, and the SiN layer serves as a blocking layer, while a PECVD SiN passivation dielectric is used to mitigate trapping effects, ensuring compatibility and minimizing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOCVD AlN is used as gate insulator and PECVD SiN as passivation dielectric, then low leakage current and high breakdown voltage are achieved, but the PECVD SiN film is degraded by the MOCVD AlN process
Solution Approach 1:
The PECVD SiN passivation dielectric is deposited first before the MOCVD AlN gate insulator. This preliminary action protects the SiN film from degradation by subsequent MOCVD processing, while still allowing the AlN to provide high breakdown voltage and low leakage current when used as the gate insulator layer.
Solution Approach 2:
The device uses a composite dielectric structure combining PECVD SiN and MOCVD AlN layers. The SiN provides passivation and mechanical protection, while the AlN provides high breakdown voltage and low leakage. The composite structure leverages the complementary strengths of both materials while managing their processing incompatibility.
2Reliability
If MOCVD AlN is used as gate insulator, then low leakage current is achieved, but processing compatibility with PECVD SiN passivation is compromised
Solution Approach 1:
The PECVD SiN passivation layer is deposited in advance before the MOCVD AlN gate insulator formation. This sequence allows the MOCVD process to proceed without degrading the SiN film quality, maintaining processing compatibility while achieving low leakage current through the AlN gate insulator.
Solution Approach 2:
The dielectric structure is segmented into distinct functional layers: PECVD SiN for passivation and MOCVD AlN for gate insulation. This segmentation allows each material to be optimized for its specific function and processed using the most suitable deposition method, resolving the processing compatibility issue.
3Reliability
If normally-off mode operation is implemented, then device safety is improved, but on-resistance increases and output-current decreases
Solution Approach 1:
The device uses parameter optimization in the AlGaN barrier layer composition and thickness to achieve normally-off operation with reduced on-resistance. By carefully controlling the Al content and layer thickness, the threshold voltage is adjusted to enable normally-off operation while minimizing the increase in on-resistance.
Solution Approach 2:
The composite structure of AlGaN barrier layer with optimized composition and MOCVD AlN gate insulator enables normally-off operation with acceptable on-resistance. The high quality interface and energy barrier provided by the AlN layer help maintain low resistance while ensuring safe normally-off operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low gate leakage, high mobility, and a breakdown voltage greater than 600 volts with minimal on-resistance degradation, enabling efficient operation of III-nitride transistors in high-power applications.
Implementation Method 1
the single-crystalline AlN provides a high-quality interface and energy barrier
Implementation Method 2
the SiN layer serves as a blocking layer
Implementation Method 3
a PECVD SiN passivation dielectric is used to mitigate trapping effects
Implementation Method 4
forming a gate electrode filling the second trench
Data Source
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AI summary
A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.