Alpha-Silicon Hard Mask for Nanoscale Dielectric Patterning

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Solution Overview

Problem

The Zep 520 positive electron beam photoresist is unsuitable for reactive ion etching using fluorine-based plasma, as it reacts and causes plastic flow, destroying nanoscale patterns in dielectric layers during the etching process.

Innovation Solution

A method involving the deposition of an α-Si film, transfer of patterns from a photoresist mask to the α-Si film using chlorine-based plasma, and subsequent use of the α-Si film as a hard mask for fluorine-based plasma etching to create nanoscale recesses in the dielectric layer, while ensuring the photoresist mask is removed without damaging the patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If Zep 520 positive EB photoresist is used for high-resolution nanoscale patterning, then pattern resolution is improved, but the photoresist reacts with fluorine-based plasma causing plastic flow and pattern destruction

Engineering Contradiction:
Improvepattern resolutionVSAvoidpattern integrity during etching
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

An α-Si film is introduced as an intermediary layer between the Zep 520 photoresist and the fluorine-based plasma etching process. The photoresist first patterns the α-Si film via chlorine-based plasma etching, then the α-Si film serves as a protective mask during subsequent fluorine-based plasma etching of the dielectric layer, preventing direct contact between the photoresist and fluorine-based plasma.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If an intermediate layer is added to protect the photoresist, then pattern integrity is improved, but process complexity increases

Engineering Contradiction:
Improvepattern integrityVSAvoidprocess steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The method utilizes different plasma chemistry parameters (chlorine-based vs. fluorine-based plasma) to achieve selective etching. The α-Si film is selectively etched by chlorine-based plasma while being resistant to fluorine-based plasma, enabling the photoresist to be removed after pattern transfer without damaging the final nanoscale patterns in the dielectric layer.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method allows for high-resolution, accurate transfer of patterns from the photoresist to the dielectric layer, maintaining pattern integrity and compatibility with conventional CMOS processes, thereby addressing the limitations of using Zep 520 photoresist in fluorine-based plasma etching.

Implementation Method 1

depositing a layer of α-Si film on a dielectric layer to be processed

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

etching the α-Si film by chlorine-based plasma with the photoresist mask

Methodology Applied
Scientific EffectPlasma etching: Plasma

Implementation Method 3

etching the dielectric layer by the fluorine-based plasma with the α-Si film as a hard mask

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS8338084B2Patterning method
Publication Date: 2012.12.25 INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
  • US8338084B2 patent drawing

AI summary

A method of patterning a dielectric layer with a Zep 520 positive EB photoresist as a mask, comprising the steps of depositing an α-Si film on the dielectric layer; providing a layer of Zep 520 positive EB photoresist having high-resolution patterns therein by electron beam direct writing; etching the α-Si film by chlorine-based plasma with the layer of Zep 520 positive EB photoresist as a mask, so as to transfer the high-resolution patterns of the Zep 520 positive EB photoresist to the underlying α-Si film; removing the Zep 520 positive EB photoresist; etching the dielectric layer by fluorine-based plasma with the α-Si film having high-fidelity patterns as a hard mask, so as to provide patterns of recesses; and removing the α-Si film by wet etching or dry etching. The inventive method is completely compatible with and easily incorporated into the conventional CMOS processes, with high reliability and resolution for providing nanoscale fine patterns of recesses. It solves the above-mentioned problem in the fabrication of novel structure of CMOS device.