Alternate Via Spacing Layout for Lower Parasitic Resistance
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Solution Overview
Problem
As chip dimensions scale down, parasitic resistances of vias on the chip increase, negatively impacting performance, and existing via layouts that use minimum spacing between vias on the same net lead to exclusion zones on neighboring nets, restricting via parallelization and increasing parasitic resistance across all terminals of a transistor.
Innovation Solution
Implementing a via layout that uses non-minimum spacing for vias on the same net, allowing for parallelization of vias on neighboring nets, which reduces parasitic resistance by removing exclusion zones and enabling more efficient electrical coupling between metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum via spacing is used to increase via parallelization, then via density increases, but exclusion zones are created on neighboring nets that restrict via placement and increase resistance
Solution Approach 1:
The patent applies different via spacing strategies to different nets based on their local requirements. Nets with high via density requirements use minimum spacing, while neighboring nets use relaxed spacing to avoid exclusion zones. This localized differentiation allows each net to optimize its own via placement without negatively impacting adjacent nets, resolving the contradiction between via density and resistance.
Solution Approach 2:
The patent segments the chip layout into different net regions, allowing independent via spacing optimization for each net. By dividing the overall via placement strategy into net-specific segments, the design can apply minimum spacing to some nets while using relaxed spacing on others, thereby achieving high via density where needed without creating problematic exclusion zones on neighboring nets.
2Length of moving object
If via dimensions are scaled down to match chip scaling, then chip size decreases, but parasitic resistance of vias increases
Solution Approach 1:
The patent changes the spacing parameter from the conventional minimum value to a relaxed value for specific nets. This parameter change allows vias to be placed with greater separation on certain nets, reducing the parasitic resistance effects that would otherwise result from high-density minimum-spacing via arrangements, thereby compensating for the resistance increase caused by overall via dimension scaling.
Data Source
AI summary
A chip includes a first net, and a second net, wherein the first net and the second net are formed from a same metal layer, and the second net neighbors the first net. The chip also includes first vias disposed on the first net, and second vias disposed on the second net. A first spacing is greater than a second spacing, the first spacing is between a first one of the first vias and a second one of the first vias, the first one of the first vias and the second one of the first vias are adjacent, and the second spacing is between the first one of the first vias and one of the second vias closest to the first one of the first vias.