Alternating DAC Architecture for Low-Jitter Delta-Sigma ADCs
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Solution Overview
Problem
Delta-sigma analog to digital converters (ADCs) are sensitive to clock jitter and dynamic error, which increase with higher sampling frequencies, leading to inaccuracies in signal conversion.
Innovation Solution
Incorporating alternately updated digital to analog converters (DACs) that operate at half the sample rate, reducing the frequency of transistor transitions and minimizing the impact of clock jitter and dynamic error, while also introducing an analog finite impulse response (AFIR) filter effect to mitigate noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling frequency is increased to improve signal conversion accuracy, then the signal conversion accuracy is improved, but the sensitivity to clock jitter and dynamic error increases
Solution Approach 1:
The patent divides the single DAC operation into two separate DACs operating alternately at half the sampling frequency. Each DAC handles alternating samples, which segments the high-frequency operation into two lower-frequency operations, reducing the impact of clock jitter and dynamic error while maintaining the overall high sampling rate performance
Solution Approach 2:
The patent implements periodic action by having two DACs operate alternately at half the sampling frequency. The first DAC operates during even clock cycles and the second DAC operates during odd clock cycles, creating a periodic pattern that maintains the effective sampling rate while reducing instantaneous transition frequency and associated errors
2Measurement precision
If the DAC operates at full sample rate to maintain signal fidelity, then the signal fidelity is maintained, but the power consumption increases
Solution Approach 1:
The patent uses periodic action by alternating between two DACs at half the full sampling frequency. Each DAC is active only during alternate clock cycles, which reduces the average power consumption compared to a single DAC operating continuously at full speed, while maintaining signal fidelity through the alternating operation pattern
Solution Approach 2:
The patent segments the full-sample-rate DAC operation into two half-rate DACs that operate alternately. This segmentation allows each DAC to operate at lower power while collectively maintaining the required sampling rate and signal fidelity, thereby reducing overall power consumption
Data Source
AI summary
A modulator of an analog to digital converter includes a quantizer component configured to generate a digital signal based on a clock input operating at a sample rate. The modulator further includes a first digital to analog converter (DAC) configured to generate first DAC output at half the sample rate. The modulator further includes a second DAC configured to generate second DAC output at half the sample rate, where the first DAC and the second DAC are updated at alternate cycles of the clock input.