Alternating Diagonal Via Structure for Uniform IC Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated circuit (IC) manufacturing processes face challenges in achieving uniform via spacing and efficient routing due to the complexity of interconnect structures and the need for precise alignment of metal tracks, which can lead to non-uniform via spacing and reduced manufacturing yields.
Innovation Solution
The implementation of a continuous diagonal via pattern in IC layout diagrams and photo masks, where via regions are positioned along alternating diagonal grid lines, and metal rules are applied to adjacent metal layers to enhance routing efficiency and pattern uniformity, improving the alignment and spacing of via structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional interconnect routing methods are used with complex metal layers, then routing functionality is achieved, but via spacing uniformity deteriorates and manufacturing precision decreases
Solution Approach 1:
The patent segments the via structures into two distinct types: mandrel vias (formed first with uniform spacing) and plug vias (formed later to fill remaining spaces). This segmentation allows each via type to be optimized independently for uniformity and functionality, resolving the contradiction between manufacturing precision and routing complexity
Solution Approach 2:
The patent performs preliminary formation of mandrel vias with controlled uniform spacing before forming the plug vias. This preliminary action establishes a uniform baseline pattern that simplifies subsequent manufacturing steps and ensures consistent via spacing across the substrate
2Productivity
If more via structures are added to improve routing efficiency, then electrical connections between metal layers are enhanced, but alignment complexity and manufacturing difficulty increase
Solution Approach 1:
The patent introduces mandrel vias as intermediary structures that serve as templates and alignment references for subsequent plug via formation. These mandrel vias act as a mediating layer that simplifies the alignment process for the complete via structure, enabling high routing efficiency without proportionally increasing manufacturing difficulty
Solution Approach 2:
The patent creates regions of uniform via spacing (equipotential regions) through the systematic arrangement of mandrel and plug vias. This equipotential approach ensures that all via locations maintain consistent spacing relationships, simplifying alignment requirements while maximizing routing capacity
Data Source
AI summary
An integrated circuit (IC) structure includes a plurality of first metal segments in a first metal layer of a semiconductor substrate, the plurality of first metal segments corresponding to first tracks, a plurality of second metal segments in a second metal layer of the semiconductor substrate adjacent to the first metal layer, the plurality of second metal segments corresponding to second tracks perpendicular to the first tracks, and a plurality of via structures configured to electrically connect the plurality of first metal segments to the plurality of second metal segments. Locations of intersections of the first and second tracks define a grid including a first plurality of diagonal grid lines alternating with a second plurality of diagonal grid lines, the first plurality of diagonal grid lines includes at least three via structures of the plurality of via structures positioned at contiguous intersection locations, and the second plurality of diagonal grid lines is free from including a via structure of the plurality of via structures.