Alternating Gate Driver Layout for Lower-Power Display Panels
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Solution Overview
Problem
The increase in the number of stages in gate drivers leads to increased power consumption and area requirements in display devices, resulting in larger dead spaces.
Innovation Solution
Implementing a gate driver design where stages are alternately arranged in a direction, sharing clock signals, and connected to an even number of pixel rows, reducing the number of stages and minimizing power consumption and area, utilizing a dual arrangement of gate drivers, and connected to an even number of pixel rows, thereby optimizing power and space efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of stages in gate drivers is increased, then the gate signals coverage is improved, but power consumption increases
Solution Approach 1:
The patent merges the clock signal generation function into a shared resource among multiple gate drivers. Instead of each gate driver having its own independent clock signal, multiple gate drivers share a common clock signal, reducing the total number of clock signals and associated power consumption while maintaining the ability to drive multiple pixel rows through alternative staging arrangements
2Adaptability or versatility
If the first to nth gate drivers are arranged in a row direction, then the gate signals coverage is improved, but area increases
Solution Approach 1:
The patent transitions from a one-dimensional row arrangement of gate drivers to a two-dimensional alternative staging arrangement. Gate drivers are organized in alternative stages that can be spatially distributed, allowing coverage of multiple pixel rows while reducing linear extension and dead space in the display device
3Adaptability or versatility
If the first to nth gate drivers are arranged in a row direction, then the gate signals coverage is improved, but dead space increases
Solution Approach 1:
By organizing gate drivers in alternative stages rather than a simple row arrangement, the patent reduces the linear footprint and dead space. The alternative staging allows for more compact spatial distribution of gate driver components, minimizing the non-active area in the display device while maintaining comprehensive pixel row coverage
Data Source
AI summary
A display device includes a display panel having a plurality of pixel rows arranged in a first direction and each including a plurality of pixels, a first gate driver including a first stage having a first gate signal as a first output to each of the plurality of pixel rows, and a second gate driver including a second stage having a second gate signal as a second output to each of the plurality of pixel rows, the second stage being alternately arranged with the first stage in the first direction. The first gate driver and the second gate driver share a first clock signal. Each of the first stage and the second stage is connected to at least four pixel rows among the plurality of pixel rows.