Alternating Gate Driver Layout for Lower-Power Display Panels
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Solution Overview
Problem
High power consumption in display apparatuses due to high frequency applied to display panel drivers.
Innovation Solution
The display apparatus is designed with gate and emission drivers alternately located on opposite sides of the display panel, reducing the frequency of clock signals applied to these drivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high frequency is applied to display panel driver, then display performance is improved, but power consumption is increased
Solution Approach 1:
The gate driver is divided into multiple gate stage groups (first gate stage group, second gate stage group, third gate stage group, fourth gate stage group) that are alternately located on opposite sides of the display panel. Each group processes different pixel rows independently, allowing parallel operation and reduced clock frequency requirements while maintaining display performance.
Solution Approach 2:
The driver architecture transitions from a single-sided sequential processing approach to a multi-sided parallel processing approach. By alternating gate stage groups on opposite sides of the panel, the system adds spatial dimensionality to the processing architecture, enabling simultaneous operation of multiple driver stages and reducing the time pressure on clock signal frequency.
2Device complexity
If gate drivers are located on one side of display panel, then device complexity is reduced, but clock signal period is shortened increasing power consumption
Solution Approach 1:
The gate stage groups are asymmetrically distributed across opposite sides of the display panel rather than being concentrated on one side. This asymmetric spatial arrangement allows for optimized signal routing and enables longer clock signal periods by distributing the driving function across multiple locations, thereby reducing power consumption without significantly increasing overall system complexity.
Data Source
AI summary
A display apparatus may include a display panel including a pixel, a gate driver configured to output gate signals to the display panel, and including a first gate stage group for generating a first gate signals, and including a first gate odd stage group on a first side of the display panel, and a first gate even stage group on a second side of the display panel, and a second gate stage group for generating a second gate signals, and including a second gate odd stage group on the second side, and a second gate even stage group on the first side, and a data driver configured to apply a data voltage to the display panel.