Alternating Hold Capacitor Circuit for Faster Sample Settling
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Solution Overview
Problem
Traditional sample and hold circuits experience reset periods where the output returns to zero, limiting their performance in high-speed applications due to the need for multiple capacitors to be coupled to the operational amplifier during hold phases, which increases load and slows down settling times.
Innovation Solution
A sample and hold circuit design utilizing three capacitors and twelve switches, operating in two phases, where only two capacitors are coupled to the operational amplifier at any given time, allowing for faster settling and eliminating reset periods by alternately holding and resetting the capacitors, thereby reducing slew rate requirements and operational amplifier load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If multiple capacitors are coupled to the operational amplifier during hold phases, then the sample and hold circuit can maintain output voltage, but the load on the operational amplifier increases and settling time increases
Solution Approach 1:
The patent divides the capacitor array into multiple groups that are sequentially coupled to the operational amplifier. During the hold phase, only a subset of capacitors (e.g., half) are connected to the operational amplifier while others are disconnected and held at fixed voltages. This segmentation reduces the instantaneous load on the operational amplifier, allowing faster settling while maintaining the ability to reconstruct the full output voltage through the combined charge stored across all capacitors.
2Use of energy by moving object
If traditional sample and hold circuits operate with reset periods, then capacitors can be recharged, but the output returns to zero limiting high-speed application performance
Solution Approach 1:
The patent implements a continuous hold mode where the output voltage is maintained throughout the entire operating cycle without returning to zero. During the hold phase, capacitors are recharged in the background while maintaining the output voltage through the operational amplifier and feedback network. This eliminates idle reset periods and allows the circuit to continuously serve high-speed applications without interruption or output dropout.
3Quantity of substance
If multiple capacitors are coupled to the operational amplifier, then charge storage capacity increases, but the load on the operational amplifier increases reducing slew rate
Solution Approach 1:
The patent dynamically controls the coupling of capacitors to the operational amplifier using switch arrays. During the sampling phase, capacitors are connected in parallel to the operational amplifier to maximize charge storage capacity. During the hold phase, the switch arrays reconfigure to connect only a subset of capacitors to the operational amplifier, reducing the load and allowing faster voltage changes (higher slew rate). The system dynamically transitions between these states to optimize both charge storage and response speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the sample and hold circuit to operate effectively in high-speed applications by maintaining the sampled voltage without reset periods, reducing load on the operational amplifier, and allowing for quicker output settling, making it suitable for sub-sampling and non-sub-sampling applications.
Implementation Method 1
a first capacitor samples an input analog signal while an electrically isolated second capacitor and the operational amplifier hold a voltage from a previous second phase at the output of the sample and hold circuit
Data Source
AI summary
A sample and hold circuit is provided. The circuit includes a plurality of switches, a first capacitor, an operational amplifier having a first input selectively coupled to the first capacitor and an output, a second capacitor and a third capacitor both selectively coupled to the first capacitor and both selectively coupled between the first input of the operational amplifier and the output of the operational amplifier, wherein the plurality of switches are configured to receive a plurality of control signals such that the first capacitor is configured to sample an input signal in a sample phase and to transfer a charge to one of the second capacitor and the third capacitor in a hold phase, and the second capacitor and third capacitor are configured to alternate between holding the transferred charge and resetting in any back-to-back hold phases.