Alternating Insulating Layers for Semiconductor Warpage Control
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Solution Overview
Problem
Semiconductor packages with build-up interconnect structures face issues of warpage and delamination due to coefficient of thermal expansion (CTE) mismatches, leading to reduced reliability and manufacturing yield, as well as increased costs.
Innovation Solution
The method involves forming a semiconductor device with alternating insulating layers of different materials, each optimized for adhesion and mechanical strength, to create a dielectric gradient that mitigates stress during temperature cycling and enhances adhesion between layers, thereby reducing warpage and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a build-up interconnect structure with insulating layers is formed over a semiconductor die, then electrical interconnection is achieved, but warpage and delamination occur due to CTE mismatches between adjacent surfaces
Solution Approach 1:
The patent applies parameter changes by carefully selecting and optimizing the coefficient of thermal expansion (CTE) values of different insulating layers. The first insulating layer is formulated with a CTE between 50-150 ppm/°C to match the semiconductor die, while the second insulating layer has a CTE between 150-300 ppm/°C to match the encapsulant. This gradient in CTE parameters eliminates thermal stress during temperature cycling, preventing both warpage and delamination while maintaining reliable electrical interconnection.
2Strength
If insulating layers are formed with non-optimal curing profile, then manufacturing process is simplified, but tensile strength and adhesion are reduced
Solution Approach 1:
The patent applies local quality by implementing a multi-stage curing profile tailored to each insulating layer's specific material properties. The first insulating layer is cured at a first temperature range optimized for its composition, followed by the second insulating layer cured at a second temperature range. This localized optimization of curing parameters for each layer maximizes tensile strength and adhesion without requiring excessive process complexity.
3Reliability
If alternating insulating layers of different materials are formed, then adhesion and mechanical strength are enhanced, but device structure becomes more complex
Solution Approach 1:
The patent applies composite materials by forming a multi-layer insulating structure where the first insulating layer and second insulating layer are made of different materials with complementary properties. The first layer provides excellent adhesion to the semiconductor die with matched CTE, while the second layer provides compatibility with the encapsulant and enhanced mechanical strength. This composite approach enhances overall reliability and adhesion while maintaining a manageable structural complexity through systematic material selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more reliable semiconductor package with improved mechanical and chemical strength, reduced warpage, and increased manufacturing yield, while minimizing costs by using a standardized carrier size for processing diverse semiconductor die sizes.
Implementation Method 1
The insulating layers are subject to cracking, particularly during temperature cycling tests, due to coefficient of thermal expansion (CTE) mismatches between adjacent surfaces.
Data Source
AI summary
A semiconductor device has a build-up interconnect structure including a first insulating layer with a first material and a second insulating layer with a second material. A first conductive layer is formed over the first insulating layer, and the second insulating layer is formed over the first conductive layer. An optional third insulating layer has the second material and is formed over the second insulating layer. A fourth insulating layer has the first material and is formed over the third insulating layer. The second, third, and fourth insulating layers are cured sequentially or simultaneously. The first material includes a greater tensile strength, elastic modulus, and CTE than the second material. The build-up interconnect structure is formed over a semiconductor wafer or semiconductor die in a reconstituted panel. Alternatively, the build-up interconnect structure is formed over a carrier and a semiconductor die is mounted over the build-up interconnect structure.