Alternating Multi-Layer Bit Line Structure for SRAM Noise Reduction
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Solution Overview
Problem
Conventional bit-line coupling noise in SRAM cell designs poses a significant challenge, requiring increased signal charge storage and leading to inefficiencies, as existing methods to reduce noise, such as inserting circuit structures or twisted bit lines, increase cell area and manufacturing costs.
Innovation Solution
A bit line structure with an alternating two-layer design, where bit lines consist of multiple first and second portions extending in an alternating manner, with the first portions in a first dielectric layer and the second portions in a second dielectric layer, significantly increasing spacing between bit lines, effectively reducing coupling noise without increasing cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional bit lines are fabricated at the same metal level with minimum line and spacing design rules, then manufacturing precision is improved, but bit-line coupling noise increases
Solution Approach 1:
The patent applies dimensionality change by transitioning bit lines from a single-plane (2D) layout to a multi-layer (3D) stacked configuration. First portions of bit lines are placed in one metal layer while second portions are placed in an adjacent metal layer, creating vertical separation between complementary bit line pairs (BL and BL-bar). This spatial reconfiguration in the vertical dimension significantly reduces capacitive coupling noise while maintaining minimum lateral spacing design rules for manufacturing precision.
2Object-generated harmful factors
If spacing between bit lines is increased to reduce coupling noise, then bit-line coupling noise is reduced, but cell area increases
Solution Approach 1:
The invention resolves the area-noise tradeoff by utilizing the vertical dimension through multi-layer metal stacking. Complementary bit lines are separated in the vertical direction (different metal layers) rather than requiring increased lateral spacing. This allows minimum lateral spacing to be maintained for area efficiency while achieving noise reduction through vertical separation, effectively decoupling the area and noise parameters.
Solution Approach 2:
The bit line structure is segmented into first portions and second portions that are spatially separated in different metal layers. This segmentation allows each portion to be optimally positioned to minimize coupling, with first portions in one layer and second portions in another layer, achieving noise reduction without lateral expansion of the cell area.
3Object-generated harmful factors
If twisted bit lines design is used to reduce coupling noise, then coupling noise is reduced, but device complexity increases
Solution Approach 1:
The patent replaces the complex twisted bit line configuration with a simpler multi-layer stacked arrangement. Instead of twisting conductors in the same plane, the invention uses vertical stacking of metal layers with straightforward planar patterns in each layer. This dimensional approach achieves equivalent or superior noise reduction with significantly reduced structural complexity and easier manufacturing.
Data Source
AI summary
A bit line structure for two-transistor static random access memory (2T SRAM), including multiple bit lines extending over multiple 2T SRAMs in a first direction, wherein each bit line consists of multiple first portions and second portions extending in the first direction and electrically connecting with each other in an alternating manner, and the first portions and the second portions are in a first dielectric layer and a second dielectric layer respectively, and the first portions of each bit line correspond to the second portions of adjacent bit lines.