Alternating Polarity Capacitive Array for Linearity
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Solution Overview
Problem
Conventional fringe capacitors in integrated circuits suffer from large linearity errors due to capacitance mismatch and parasitic capacitance issues, making them unsuitable for applications requiring good linearity, such as capacitive digital-to-analog converters (CDACs).
Innovation Solution
An alternating polarity capacitive array is implemented with compensation fingers added at specific locations to compensate for capacitance mismatch, improving linearity, and the array is split into segments with scaling capacitors and shielding structures to minimize parasitic capacitance, along with a dispersed connection pattern for unit capacitors to enhance capacitance matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional fringe capacitors are used in high density arrays, then capacitive density is improved, but linearity deteriorates due to capacitance mismatch and parasitic capacitance
Solution Approach 1:
The capacitive array is divided into multiple segments with alternating polarity groups. Each segment contains capacitors with the same polarity, and adjacent segments have opposite polarities. This segmentation allows for better control of parasitic capacitance effects and improves linearity while maintaining high density through the alternating pattern.
Solution Approach 2:
Different regions of the capacitive array are assigned different polarities to create localized electrical characteristics. The alternating polarity arrangement ensures that edge effects and parasitic capacitances are distributed uniformly across the array, compensating for mismatch errors that would otherwise occur at boundaries between capacitors.
2Manufacturing precision
If compensation fingers are added to alternating polarity capacitive structures, then linearity is improved, but device complexity increases
Solution Approach 1:
The compensation fingers are merged with the existing capacitive structure by integrating them as additional interdigitated fingers within the same alternating polarity segments. This approach provides linearity compensation without requiring separate compensation structures, thereby limiting the increase in device complexity.
3Area of stationary object
If capacitors are arranged in high density arrays, then footprint is reduced, but parasitic capacitance increases
Solution Approach 1:
The alternating polarity arrangement converts the harmful parasitic capacitance between adjacent capacitors into a beneficial compensation mechanism. By alternating polarities, the parasitic capacitances are distributed and partially cancel each other out, transforming what would be a source of error into a means of improving linearity and measurement accuracy.
Data Source
AI summary
Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.