Alternating Read Mode for Non-Volatile Memory Cells
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Solution Overview
Problem
The coupling between adjacent floating gates in non-volatile semiconductor memory devices, such as EEPROM and flash memory, leads to erroneous readings due to shifts in the apparent charge stored, which is more pronounced in multi-state devices with narrower threshold voltage ranges, and is exacerbated by shrinking memory cell sizes and reduced spacing between word and bit lines.
Innovation Solution
The read process for a targeted memory cell includes compensating for the coupling effect by intermixing read operations with those of neighboring memory cells, applying different voltages based on the condition of the neighbor cells to accurately determine the data stored in the target cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced and spacing between word and bit lines is decreased to increase storage density, then storage capacity is improved, but coupling between adjacent floating gates increases causing reading errors
Solution Approach 1:
The patent applies preliminary action by performing read operations on neighboring memory cells before reading the target memory cell. This preliminary read establishes the charge state of adjacent floating gates, allowing the system to compensate for their coupling effect on the target cell's reading, thereby maintaining reading accuracy despite reduced spacing
Solution Approach 2:
The patent changes operating parameters by applying different voltages to control gates and bit lines during read operations depending on the state of neighboring cells. By dynamically adjusting these voltage parameters based on neighboring cell conditions, the system compensates for coupling effects and maintains reliable readings at higher storage densities
2Quantity of substance
If multiple distinct threshold voltage ranges are used to store multiple data bits per cell, then storage capacity is improved, but the narrower ranges make readings more susceptible to coupling effects
Solution Approach 1:
The patent implements feedback by using the read results from neighboring memory cells to adjust the reading process for the target cell. The system monitors the charge states of adjacent floating gates and uses this information to compensate for their influence, ensuring accurate threshold voltage measurements even in multi-state devices with narrow ranges
Solution Approach 2:
The patent replaces direct threshold voltage measurement with a compensated measurement approach. Instead of directly measuring the threshold voltage and being affected by coupling, the system substitutes this with a two-step process: first reading neighboring cells, then using that information to adjust and compensate the target cell reading, eliminating the direct coupling effect
3Speed
If read operations are performed on target memory cells without compensating for neighboring cell effects, then reading speed is maintained, but data accuracy deteriorates due to floating gate coupling
Solution Approach 1:
The patent merges the read operations of target and neighboring memory cells into a coordinated sequence. By combining these operations and executing them in an interleaved manner, the system maintains high throughput while ensuring that neighboring cell states are accounted for, thus preserving both speed and accuracy
Solution Approach 2:
The patent applies periodic action by alternating between reading target cells and reading neighboring cells in a systematic sequence. This periodic pattern ensures that compensation information is gathered at regular intervals, maintaining reading accuracy without significantly impacting overall reading speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the impact of floating gate to floating gate coupling, enhancing the accuracy of data reading in multi-state devices by accounting for the charge stored in neighboring cells, thereby maintaining data integrity and reliability even as memory cells shrink and spacing decreases.
Implementation Method 1
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate.
Implementation Method 2
Shifts in the apparent charge stored on a floating gate can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates.
Data Source
AI summary
Shifts in the apparent charge stored on a floating gate (or other charge storage element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other charge storing elements). To account for this coupling, the read process for a targeted memory cell will provide compensation to an adjacent memory cell (or other memory cell) in order to reduce the coupling effect that the adjacent memory cell has on the targeted memory cell. The compensation applied is based on a condition of the adjacent memory cell. To apply the correct compensation, the read process will at least partially intermix read operations for the adjacent memory cell with read operations for the targeted memory cell.