Alternating Semiconductor Chip Stacking for Memory Capacity
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Solution Overview
Problem
The increasing number of stacked semiconductor chips in memory devices leads to enlarged device size and higher manufacturing costs, as existing methods do not efficiently optimize chip arrangement and interconnection for reduced size and cost.
Innovation Solution
A semiconductor device design featuring alternately stacked first and second semiconductor chips, with via-contacts connecting them to a logic chip and external circuits, and a manufacturing method that bonds wafers with functional layers alternately arranged to minimize device height and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked semiconductor chips is increased to enlarge memory capacity, then the memory capacity is improved, but the device size is enlarged and manufacturing cost increases
Solution Approach 1:
The patent transitions from a conventional single-column vertical stacking arrangement to a two-dimensional array stacking structure where memory chips are arranged in multiple columns and stacked alternately with different chip types (e.g., memory chips and buffer chips). This dimensional change allows memory capacity to scale across multiple stacking columns rather than requiring a single tall stack, thereby increasing capacity while controlling the height and footprint of each individual stacking column, effectively managing overall device size.
2Quantity of substance
If the number of stacked semiconductor chips is increased to enlarge memory capacity, then the memory capacity is improved, but the manufacturing cost increases
Solution Approach 1:
The patent segments the memory device into multiple independent stacking columns, where each column functions as a separate modular unit. Each stacking column can be manufactured, tested, and assembled independently using standardized processes. This segmentation enables parallel manufacturing of multiple columns, improving production efficiency and reducing per-unit manufacturing costs while achieving high total memory capacity through the aggregation of multiple columns.
Solution Approach 2:
The patent employs universal buffer chips that can be alternately stacked with different types of memory chips (e.g., first memory chips and second memory chips) in different stacking columns. These buffer chips serve multiple functions: electrical connection between memory chips, signal routing, and compatibility interface. This multi-functionality reduces the variety of unique chip designs needed, simplifying the manufacturing process and reducing costs associated with designing and producing multiple specialized chip types.
3Length of stationary object
If wafers are bonded with functional layers alternately arranged, then the device height is minimized, but the manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-arranging functional layers (such as connection terminals and conductive patterns) on the wafers before the bonding process. The wafers are prepared with predetermined functional layer configurations that match the alternating stacking pattern. This preliminary preparation ensures that when wafers are bonded in alternating sequences, the functional layers align correctly without requiring complex real-time adjustment during assembly, thereby minimizing device height while keeping manufacturing complexity manageable through pre-planned layer arrangements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the size and manufacturing cost of semiconductor devices by optimizing chip stacking and interconnection, allowing for efficient electrical connections and simplified manufacturing processes.
Implementation Method 1
bonds wafers with functional layers alternately arranged
Data Source
AI summary
A semiconductor device includes a base member; a first stacked body including first semiconductor chips and second semiconductor chips stacked alternately in a first direction crossing a front surface of the base member; and a second stacked body arranged with the first stacked body in a second direction along the front surface of the base member. The second stacked body includes other first semiconductor chips and other second semiconductor chips stacked alternately in the first direction. The first stacked body includes a lowermost first semiconductor chip connected to the base member, and the second stacked body includes a lowermost second semiconductor chip connected to the base member.