Alternating Shift-Register Gate Circuit for Flexible Resolution
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Solution Overview
Problem
Traditional gate driving circuits with cascaded shift registers face limitations in achieving flexible display resolutions, particularly in transitioning between high and low resolutions without compromising display quality.
Innovation Solution
A gate driving circuit design with alternating cascaded first and second shift registers, controlled by specific clock signals and reset configurations, allowing for flexible resolution switching through sequential and synchronized output signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a traditional gate driving circuit with cascaded shift registers is used, then the circuit structure is simple, but the display resolution flexibility is limited
Solution Approach 1:
The gate driving circuit is divided into multiple independent shift register units (first shift register and second shift register) that can operate independently. Each shift register unit can be selectively activated to drive different numbers of pixel rows, enabling flexible resolution switching between full resolution and low resolution modes without requiring a completely different circuit architecture.
Solution Approach 2:
The circuit incorporates dynamic control mechanisms where the number of active shift register units and the timing of clock signals can be adjusted based on the desired display resolution. The system can dynamically switch between different operating modes (full resolution with all shift registers active, low resolution with selective activation) to adapt to different display requirements.
2Ease of operation
If all shift registers are activated for full resolution display, then display quality is maintained, but switching to low resolution is complex
Solution Approach 1:
The circuit includes preliminary reset mechanisms and pre-configured clock signal generation that prepare the shift register units for different operating modes before resolution switching is required. The reset signals can be selectively applied to specific shift register units to ensure they are in the correct initial state before being activated for a particular resolution mode, facilitating smooth and reliable switching.
Solution Approach 2:
The system incorporates feedback mechanisms where the control circuit monitors the operating mode and adjusts the activation of shift register units and timing of clock signals accordingly. This feedback ensures that the correct number of shift register units are activated and synchronized to maintain display quality consistency across different resolution modes.
3Adaptability or versatility
If multiple independent shift register units are used, then resolution flexibility is improved, but clock signal control becomes complex
Solution Approach 1:
The control circuit generates periodic clock signals with adjustable duty cycles that are distributed to different shift register units in a coordinated manner. By using periodic clock signals with controlled timing and duty cycles, the system can synchronize multiple independent shift register units for full resolution operation or selectively activate subsets for low resolution modes, managing the complexity of multi-unit coordination through rhythmic timing patterns.
Data Source
AI summary
There is provided a gate driving circuit, a display panel and a driving method of the gate driving circuit. The gate driving circuit includes multiple stages of shift registers. The multiple stages of shift registers comprise N first shift registers arranged alternately with N second shift registers. The N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals. The N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals. K and N are both integers greater than 1, and K≤N.