Alternating Source Region Arrangement for LDMOS Snapback Prevention
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Solution Overview
Problem
Power transistor devices, such as LDMOS transistors, are susceptible to snapback events due to the generation of secondary charge carriers, which limits their safe operating area and can result in device damage from high currents and voltages, and existing solutions are often costly or restrictive in terms of device size and performance.
Innovation Solution
The implementation of a composite source region with alternating constituent source regions of different dopant concentrations, along with an oppositely doped well region, reduces the risk of snapback by providing a passageway for secondary charge carriers and lowering the resistance of the parasitic bipolar transistor structure, thus increasing the safe operating area without significantly increasing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single uniformly doped source region is used, then the device structure is simple and manufacturing is easier, but the safe operating area is limited due to snapback events
Solution Approach 1:
The source region is divided into multiple alternating segments with different dopant concentrations (first和第二 constituent source regions). This segmentation allows different portions of the source to serve different functions: highly doped regions provide low resistance paths while lightly doped regions facilitate secondary charge carrier extraction, thereby expanding the safe operating area without requiring a completely new device architecture
Solution Approach 2:
Different regions within the source are assigned different dopant concentrations tailored to their specific functional requirements. The first constituent source regions have higher dopant concentrations optimized for current conduction, while the second constituent source regions have lower dopant concentrations optimized for extracting secondary charge carriers. This local differentiation resolves the contradiction by allowing each region to be optimized for its specific purpose rather than using a uniform structure
2Reliability
If the source region is designed to prevent snapback events, then device reliability improves, but on-resistance increases
Solution Approach 1:
The alternating segmented structure provides multiple parallel conduction paths through the highly doped first constituent source regions, maintaining low on-resistance. Simultaneously, the lightly doped second constituent source regions provide dedicated paths for extracting secondary charge carriers, preventing snapback. The segmentation thus enables both snapback prevention and low resistance through parallel functional pathways
Solution Approach 2:
The dopant concentration parameter is varied spatially across the source region to achieve different electrical characteristics in different areas. By changing the dopant concentration from high in first constituent regions to low in second constituent regions, the invention creates regions with different resistance characteristics that work together to simultaneously reduce overall resistance and prevent snapback
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the safe operating area of power transistor devices, allowing for a wider range of safe terminal voltage and current conditions, reduces the risk of damage from events like electrostatic discharge, and maintains relatively low on-resistance, all while being compatible with existing fabrication processes.
Implementation Method 1
The holes are eventually collected by the body terminal of the LDMOS transistor device. The composite source region may be used to address the generation of secondary charge carriers in power transistor devices
Implementation Method 2
The shallower, more lightly doped nature of the other constituent source region helps to provide a passageway for the secondary charge carriers, as described below. The passageway effectively reduces the base resistance of the parasitic bipolar transistor structure
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a body region disposed in the semiconductor substrate and having a first conductivity type, a composite source region disposed in the semiconductor substrate adjacent the body region and having a second conductivity type, and a gate structure supported by the semiconductor substrate and having a side adjacent the composite source region. The composite source region includes a plurality of first constituent source regions disposed along the side of the gate structure and having the second conductivity type, and a second constituent source region disposed along the side of the gate structure and between two first constituent source regions of the plurality of first constituent source regions, the second constituent source region having the second conductivity type. The second constituent source region has a different dopant concentration level than the plurality of first constituent source regions.