Alternating Spacer Deposition for Semiconductor Pitch Reduction
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Solution Overview
Problem
Existing semiconductor manufacturing processes face limitations in increasing feature density beyond the capabilities of optical lithography, particularly in forming features with a second pitch equal to 1/n, where n is an integer greater than 1, without reducing feature size or spacing to one-half of that attainable using lithography.
Innovation Solution
The use of alternating spacer deposition (ASD) techniques to achieve variable critical dimension (CD) reduction ratios, involving multiple spacer layers and selective etches to multiply the pattern density by n times, where n is an odd or even integer greater than 1, thereby increasing feature density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If optical lithography is used to form features, then the manufacturing process is simple and cost-effective, but the feature density is limited to the lithography resolution limit
Solution Approach 1:
The patent segments the single lithography step into multiple sequential steps: initial lithography to form first spacers, followed by alternating depositions of sacrificial and non-sacrificial spacer materials, selective etching, and removal of sacrificial layers. This segmentation allows achieving n-times density multiplication (where n is an odd or even integer greater than 1) by breaking down the complex density enhancement into manageable modular steps.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical structuring by forming multiple spacer layers at different heights and selectively etching them. This dimensional transition enables density multiplication by utilizing vertical stacking of sacrificial and non-sacrificial spacer materials, where the final pattern density is n times the original lithography mask density.
2Manufacturing precision
If feature size is reduced to achieve higher density, then feature density increases, but manufacturing precision and control become more difficult
Solution Approach 1:
The patent introduces sacrificial spacer layers as intermediary elements that mediate between the lithography-defined features and the final high-density pattern. These sacrificial layers (formed from materials like silicon dioxide or silicon nitride) are deposited conformally, patterned, and then selectively removed to reveal the underlying non-sacrificial spacers at reduced pitch. This intermediary approach enables precise CD control at n-times density without directly manipulating features at the final small dimensions.
Solution Approach 2:
The patent changes the material parameters and structural parameters through alternating depositions. By varying the spacer material composition (sacrificial vs. non-sacrificial), deposition thickness, and etch selectivity, the process achieves variable critical dimension reduction ratios. The final CD is controlled by the thickness of non-sacrificial spacer layers rather than direct lithography, enabling better CD uniformity and precision.
3Manufacturing precision
If multiple lithography masks are used to increase feature density, then feature density increases, but manufacturing cost and process time increase
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial spacer layers and non-sacrificial spacer layers in alternating sequences before the final pattern transfer. The sacrificial layers are deposited and patterned in advance, then selectively removed to create the high-density pattern. This preliminary structuring allows the final etch to directly transfer the n-times density pattern in a single step, avoiding multiple lithography cycles and improving manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ASD process effectively reduces the CD to ½m or 1/(2m−1 of the original value, significantly enhancing feature density by multiples of 2 or odd fractions, thus improving yield and reducing manufacturing costs.
Implementation Method 1
a conformal hard mask layer 20, for example silicon dioxide, is formed
Data Source
AI summary
A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.