Alternating Stress Liner for TSV Crack Prevention
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Solution Overview
Problem
The deposition of TSV liners in integrated circuits often results in stress-induced cracks or seams due to high deposition rates and thickness, leading to increased leakage paths, which worsen during the annealing process, affecting the reliability and performance of the ICs.
Innovation Solution
The use of alternating layers of dissimilar insulation films with alternating tensile and compressive stress, deposited in thin layers to relieve stress and prevent cracks, forming a sandwich-like structure that electrically insulates the conductive material from the silicon substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick liner is deposited to provide adequate insulation, then the insulating effect is improved, but stress-induced cracks and seams increase
Solution Approach 1:
The liner is divided into multiple thin alternating layers of different materials (e.g., silicon oxide and silicon nitride) with different stress characteristics. This segmentation allows each layer to be thinner and less prone to cracking while collectively providing the required insulation thickness and stress balance.
Solution Approach 2:
The liner uses composite structure with alternating layers of different dielectric materials having different mechanical and electrical properties. This composite approach enables simultaneous optimization of insulating performance and mechanical strength by selecting materials with complementary characteristics.
2Productivity
If high deposition rate is used to increase productivity, then the deposition speed is improved, but stress-induced defects increase
Solution Approach 1:
The total liner thickness is segmented into multiple thin sub-layers deposited in sequence. Each thin layer can be deposited at high speed while maintaining quality, and the alternating stress characteristics of different materials prevent crack propagation that would occur in a single thick layer.
Solution Approach 2:
The deposition parameters are optimized for each thin layer, and the alternating stress states created by different materials compensate for stress accumulation that would normally occur with high-rate deposition of thick single layers.
3Device complexity
If single-layer liner structure is used to simplify manufacturing, then the process complexity is reduced, but leakage paths increase
Solution Approach 1:
The alternating layer structure creates multiple interfaces between materials with different dielectric properties and stress states. These interfaces act as barriers to leakage paths, and the complementary stress characteristics prevent crack formation that would create leakage channels.
Solution Approach 2:
The inherent stress that would normally cause cracking is converted into a beneficial feature by alternating between tensile and compressive stress layers. The compressive layers prevent crack propagation in tensile layers, transforming what would be harmful stress into a protective mechanism against leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces leakage paths by relieving stress in the liner, enhancing the structural integrity and reliability of TSVs, thereby meeting the functional specifications of integrated circuits.
Implementation Method 1
The liner is formed by depositing two or more 0.5x thickness thermal layers and two or more 0.5x thickness compressive layers in alternating succession. By using an approach in which the tensile and compressive films are alternately deposited, stress can be relieved in the liner, which reduces or eliminates defects such as cracks or seams
Implementation Method 2
The liner deposition process on a chemical vapor deposition (CVD) platform involves deposition of a tensile thermal film followed by plasma assisted hermetic compressive oxide film as a cap
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an integrated circuit includes a silicon semiconductor substrate having one or more through-silicon vias (TSVs), although other through-body vias can be used as will be appreciated in light of this disclosure. Each TSV extends through at least a portion of the substrate, for example, from one side (e.g., top) of the substrate to the opposite side of the substrate (e.g., bottom), or from one internal layer of the substrate to another internal layer. A liner is disposed between the substrate and each TSV. The liner is formed of multiple alternating layers of dissimilar insulation films (e.g., tensile films and compressive films) sandwiched together.