Alternating Tap-Cell Strategy for Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Tap cells in integrated circuits do not scale aggressively with technology nodes when using 248 nm litho tools, leading to area consumption and increased costs due to inefficient use of space and the need for more expensive 193 nm litho tools for critical mask layers.
Innovation Solution
The arrangement of tap cells with consecutive first and second tap actives extending to well boundaries within tap columns, optimizing area usage and reducing substrate resistance, allowing for area savings and cost reduction by using cheaper lithography tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If tap cells are pre-placed at a fixed pitch using 248 nm litho tools, then manufacturing cost is reduced, but area efficiency deteriorates and scaling becomes aggressive
Solution Approach 1:
The tap cell is segmented into multiple tap actives (first tap active and second tap active) that can be independently optimized. This segmentation allows different tap actives to serve different functions: some extend to well boundaries for latch-up protection while others are optimized for area efficiency, resolving the contradiction between manufacturing simplicity and area efficiency
Solution Approach 2:
Different regions of the tap cell are assigned different qualities/functions. The first tap active extends to the first well boundary while the second tap active extends to the second well boundary, creating local optimizations that collectively improve both area efficiency and latch-up protection without requiring expensive litho tools
2Quantity of substance
If tap cells consume more area, then fewer transistors per die, but area overhead increases
Solution Approach 1:
The tap actives are arranged in a dimensional optimization where they extend to well boundaries in a manner that optimizes space utilization. By strategically positioning tap actives to reach well boundaries, the design achieves efficient space usage that increases transistor density without proportionally increasing tap cell area overhead
3Manufacturing precision
If 193 nm litho tools are used for tap cells, then manufacturing precision improves, but manufacturing cost increases
Solution Approach 1:
The tap cell design uses a standardized template that can be repeatedly copied across the chip. This copying approach allows the use of less precise but cheaper 248 nm litho tools while maintaining adequate pattern quality, as the standardized design compensates for the lower lithography precision through its inherent robustness
Data Source
AI summary
An integrated circuit includes a plurality of N wells disposed on a P substrate. A plurality of tap columns is located across the plurality of N wells and a plurality of standard cells is located between the tap columns. A plurality of tap cells is disposed consecutively in the plurality of tap columns. Each tap cell further includes a first tap active and a second tap active. The first tap active of a first tap cell extends to the first tap active of a second tap cell which further extends to a well boundary of either the first tap cell or the second tap cell. The first tap active of the first tap cell and the first tap active of the second tap cell are adjacent to each other in the tap column.