Alternating Recessed Trenches for Low-Capacitance Interconnects
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Solution Overview
Problem
As microprocessors become faster and smaller, the increasing density of integrated circuitry leads to higher line-to-line capacitance between interconnect lines, limiting performance and requiring precise alignment in masking and etching processes, which is challenging with conventional lithography.
Innovation Solution
The solution involves forming interconnect lines in alternating trenches of different depths, with the top surfaces of the first interconnect lines recessed below the top surfaces of the second interconnect lines, thereby reducing the effective distance between them and decreasing line-to-line capacitance. This approach allows for the use of higher dielectric constant materials without increasing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of interconnect lines is decreased to increase density, then the number of interconnect lines per unit area increases, but the line-to-line capacitance between neighboring interconnect lines increases
Solution Approach 1:
The patent applies local quality by creating alternating recessed and non-recessed interconnect lines, where specific lines are selectively recessed below the surface of the interlayer dielectric while others remain at the surface. This local differentiation in depth allows neighboring lines to be positioned at different vertical levels, thereby reducing the capacitive coupling between them while maintaining high lateral density.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement of interconnect lines to a three-dimensional alternating depth configuration. By utilizing the vertical dimension to create alternating recessed and non-recessed lines, the patent reduces the effective coupling area between neighboring lines while maintaining the same lateral pitch, thus reducing capacitance without sacrificing density.
2Quantity of substance
If the pitch of interconnect lines is decreased to increase density, then more interconnect lines can be formed, but the alignment precision required for masking and etching processes increases beyond conventional lithography capabilities
Solution Approach 1:
The patent applies preliminary action by forming the alternating recessed and non-recessed interconnect line structure before contact formation. The recessed lines are created in advance with greater vertical separation from the surface, which provides a built-in alignment buffer. This preliminary depth differentiation allows subsequent contact alignment to be more tolerant of lateral misalignment, as the etch selectivity between recessed and non-recessed lines provides an additional degree of freedom for alignment.
Solution Approach 2:
The patent introduces the alternating depth structure as an intermediary mechanism that mediates between the conflicting requirements of high density and precise alignment. The vertical depth difference acts as a buffer that decouples the lateral alignment precision requirements, allowing contacts to be formed with relaxed alignment tolerances while still achieving selective connection to the intended interconnect lines through etch selectivity.
3Object-affected harmful factors
If low-k dielectric materials are used to reduce line-to-line capacitance, then capacitance decreases, but the structural integrity of the interconnect structure deteriorates
Solution Approach 1:
The patent applies parameter changes by modifying the vertical depth parameter of alternating interconnect lines rather than changing the dielectric material's k-value. By recessing every other line below the surface, the patent reduces the effective capacitance through increased vertical separation and reduced overlapping area, while maintaining the structural integrity of the dielectric material. This approach avoids the mechanical weakness associated with low-k materials while achieving the desired capacitance reduction.
Data Source
AI summary
Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.