Conductive Lines with Alternating Widths for DRAM Integration
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Solution Overview
Problem
In the fabrication of integrated circuitry, particularly memory circuitry like DRAM, the increasing proximity of conductive vias to adjacent circuit components leads to undesired parasitic capacitance and misalignment issues, which can result in shorting and damage to the circuitry, affecting the reliability and performance of the integrated circuits.
Innovation Solution
The formation of horizontally-spaced conductive vias with longitudinally-alternating wider and narrower regions, where the wider regions are directly above the conductive vias and the narrower regions are between them, along with the use of recessed access devices and conductive gate structures, helps in reducing parasitic capacitance and preventing shorting by creating a controlled electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conductive vias are placed closer to adjacent circuit components to increase integration density, then productivity is improved, but parasitic capacitance increases and manufacturing precision deteriorates
Solution Approach 1:
The patent applies local quality by creating varying widths of the conductive line in different regions. The line is wider directly above the conductive via to ensure robust electrical connection, and narrower in regions between vias to reduce parasitic capacitance. This spatial variation in geometric properties optimizes both connectivity and electrical performance locally.
Solution Approach 2:
The conductive line is segmented into regions of different widths rather than maintaining a uniform cross-section. This segmentation allows the line to serve dual functions: providing strong electrical connection where needed (above vias) and minimizing capacitive coupling where not needed (between vias), thereby resolving the contradiction between integration density and parasitic capacitance.
2Productivity
If conductive vias are placed closer to adjacent circuit components to increase integration density, then productivity is improved, but manufacturing precision deteriorates due to misalignment and shorting
Solution Approach 1:
The patent incorporates a wider region of the conductive line directly above each via as a protective measure. This wider section acts as a cushion that compensates for potential misalignment during fabrication, ensuring that even if the via placement varies within tolerance ranges, the electrical connection remains intact and shorting is prevented.
Solution Approach 2:
By making the conductive line width variable rather than uniform, the patent creates localized regions of enhanced tolerance (wider areas above vias) and regions of optimized performance (narrower areas between vias). This local variation in geometric properties addresses manufacturing precision concerns while maintaining high integration density.
3Reliability
If wider conductive lines are used directly above vias to ensure robust connection, then reliability is improved, but parasitic capacitance increases
Solution Approach 1:
The conductive line is designed with non-uniform width, being wider directly above the conductive via to ensure robust electrical connection and reliability, and narrower in the regions between vias to minimize parasitic capacitance. This spatially varying geometry resolves the contradiction by optimizing each region for its specific function.
Solution Approach 2:
The conductive line is segmented into functional regions: wider segments above vias for reliable connection and narrower segments between vias for reduced capacitance. This segmentation allows the single conductive line to simultaneously achieve both high reliability and low parasitic capacitance through differentiated local properties.
Data Source
AI summary
A method used in forming integrated circuitry comprises forming horizontally-spaced conductive vias above a substrate. Conducting material is formed directly above and directly against the conductive vias. The conducting material is patterned to form individual conductive lines that are individually directly above a plurality of the conductive vias that are spaced longitudinally-along the respective individual conductive line. The patterning forms the individual conductive lines to have longitudinally-alternating wider and narrower regions. The wider regions are directly above and directly against a top surface of individual of the conductive vias and are wider in a horizontal cross-section that is at the top surface than are the narrower regions in the horizontal cross-section. The narrower regions are longitudinally-between the wider regions. Other embodiments, including structure independent of method, are disclosed.