Alternating-Width Semiconductor Layers for Reliable OTP Breakdown
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Solution Overview
Problem
Existing one-time-programmable (OTP) memory elements, such as anti-fuse bits in integrated circuits, face challenges in reliably and consistently programming the dielectric material, leading to inconsistent data retention and read operations.
Innovation Solution
The proposed solution involves a memory device with OTP memory cells that include a first transistor with a gate dielectric layer that can be reliably destroyed during programming, and a second transistor acting as a switching element to select the OTP memory cell. The gate dielectric layer of the first transistor is formed thinner than other transistors to ensure consistent breakdown, and higher programming voltages are used to increase reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a layer of dielectric material is used to form an anti-fuse bit, then non-volatile memory is provided, but programming reliability and data retention consistency are poor
Solution Approach 1:
The patent applies local quality by forming a thinner gate dielectric layer specifically for the first transistor in the OTP memory cell compared to other transistors. This localized modification ensures that the dielectric breakdown occurs reliably at the intended location with consistent characteristics, thereby improving both programming reliability and data retention consistency without affecting other components.
Solution Approach 2:
The patent changes the physical parameter of the gate dielectric layer thickness to optimize programming behavior. By reducing the thickness of the gate dielectric layer in the first transistor, the breakdown voltage is lowered and the breakdown process becomes more predictable and reliable, directly addressing the inconsistency in data retention while maintaining non-volatile memory functionality.
2Reliability
If higher programming voltages are used to increase programming reliability, then breakdown consistency improves, but power consumption increases
Solution Approach 1:
The patent changes the gate dielectric thickness parameter to achieve reliable breakdown at lower voltage levels. The thinner dielectric layer has a lower breakdown voltage, which reduces the programming voltage requirement and consequently lowers power consumption during programming operations while maintaining consistent and reliable programming across all OTP memory cells.
3Reliability
If the gate dielectric layer is formed thinner to ensure consistent breakdown, then programming reliability improves, but transistor strength decreases
Solution Approach 1:
The patent applies local quality by differentiating the gate dielectric thickness between the first transistor and other transistors in the circuit. The first transistor has a thinner gate dielectric optimized for reliable OTP programming, while other transistors maintain their original thicker gate dielectric for optimal switching performance, thus preserving overall circuit strength while achieving breakdown consistency where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reliable programming and data retention in OTP memory cells, improving the consistency of read operations and reducing power consumption by lowering the breakdown voltage of the transistors.
Implementation Method 1
a programming electric field is applied across the dielectric material layer to sustainably alter (e.g., break down) the dielectric material, thus decreasing the resistance of the dielectric material layer
Data Source
AI summary
A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.