Alternating Wiring Widths in Semiconductor Devices
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Solution Overview
Problem
Semiconductor devices with multilayered wiring structures face issues of increased size due to variability in wiring path widths and pitches, leading to abnormalities in the shape of the wiring pattern.
Innovation Solution
The semiconductor device features alternating wiring paths with one path having a wider width in the lower layer and a narrower width in the upper layer, allowing for a reduced pitch between paths, thereby maintaining a compact size without shape abnormalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the upper layer-wiring paths are offset by 2 μm or more in the width direction or the width of the lower layer-wiring paths is made greater than the upper layer-wiring paths, then abnormalities in the shape of the wiring pattern are prevented, but the pitch between wiring is increased and the device size becomes larger
Solution Approach 1:
The patent applies local quality by making the lower layer-wiring paths have different widths at different locations. Specifically, the lower layer-wiring paths have a first width in the region facing the upper layer-wiring paths and a second width (greater than the first width) in the region adjacent to the first region. This local variation in width compensates for the step effect locally without requiring global offset or uniform width increase, thus preventing wiring pattern shape abnormalities while maintaining compact device size.
2Manufacturing precision
If the pitch between wiring is increased to prevent shape abnormalities, then wiring pattern uniformity is improved, but the device size becomes larger
Solution Approach 1:
The patent uses local quality by varying the width of lower layer-wiring paths locally - narrower in the facing region and wider in the adjacent region. This localized width adjustment prevents shape abnormalities without requiring increased pitch between wiring paths, thereby avoiding increase in device length while maintaining wiring pattern uniformity.
3Ease of manufacture
If steps are generated in the surface of the interlayer insulating film according to the lower layer-wiring pattern, then the wiring structure is formed, but variability in the shape and wiring width of the upper layer-wiring pattern occurs
Solution Approach 1:
The patent applies preliminary anti-action by pre-compensating for the step effect through asymmetric width design of the lower layer-wiring paths. The lower layer-wiring paths are designed with greater width in the adjacent region compared to the facing region, which counteracts the step-induced narrowing effect before the upper layer-wiring paths are formed. This preliminary compensation prevents shape variability in the upper layer-wiring patterns while maintaining the multilayered wiring structure.
Data Source
AI summary
One wiring width of upper and lower wiring paths formed facing each other sandwiching an interlayer insulating film is large, and another wiring width is small; and the wiring widths of mutually adjacent wiring paths are formed to be large and small in alternating fashion on the same wiring layer.