Alternative Direct-Mapped Cache With Previous Miss Tag Field

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Solution Overview

Problem

Direct-mapped caches suffer from low cache hit rates due to their restrictive mapping, leading to reduced performance as multiple active main memory segments often map to the same cache entry, resulting in frequent cache misses and evictions.

Innovation Solution

The implementation of an alternative direct-mapped cache that includes a previous miss tag field and a last reference bit field, allowing for more informed cache replacement policies by tracking recent memory references and maintaining multiple tags per cache line, thereby reducing unnecessary evictions and improving hit rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional direct-mapped cache is used with single tag per cache line, then the cache structure is simple and fast, but the cache hit rate is low due to frequent evictions when multiple memory blocks map to the same cache line

Engineering Contradiction:
Improvecache hit rateVSAvoidcache structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The cache line is segmented into multiple tag fields (current tag field and previous miss tag field) to store information about multiple memory blocks that map to the same cache line. This segmentation allows the cache to track both the currently cached block and previously accessed blocks, enabling better utilization of the cache space and reducing unnecessary evictions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention adds a temporal dimension to the tag storage by introducing a previous miss tag field that records tags from prior cache misses. This transforms the single-dimension tag storage into a multi-dimensional structure that captures both current and historical access information, allowing the cache to make more informed replacement decisions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If cache entries are replaced on every miss in direct-mapped cache, then new data can be loaded, but frequently accessed data may be evicted causing performance degradation

Engineering Contradiction:
Improvedata access efficiencyVSAvoidcache hit rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The cache implementation uses feedback from previous miss tags to influence replacement decisions. When a cache miss occurs, the system checks if the requested block's tag matches the previous miss tag. If it does, the cache recognizes this as a repeated access pattern and retains the data rather than evicting it, using the feedback from historical access patterns to improve future performance.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The cache performs preliminary checking of the previous miss tag before executing a standard replacement. This preliminary action allows the system to identify and preserve frequently accessed data blocks that map to the same cache line, preventing unnecessary evictions before they occur and maintaining higher hit rates for predictable access patterns.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10176118B2Alternative direct-mapped cache and cache replacement method
Publication Date: 2019.01.08 LENOVO GLOBAL TECHNOLOGIES SWITZERLAND INTERNATIONAL GMBH
  • US10176118B2 patent drawing
  • US10176118B2 patent drawing
  • US10176118B2 patent drawing

AI summary

A method includes storing a first block of main memory in a cache line of a direct-mapped cache, storing a first tag in a current tag field of the cache line, wherein the first tag identifies a first memory address for the first block of main memory, and storing a second tag in a previous miss tag field of the cache line in response to receiving a memory reference having a tag that does not match the tag stored in the current tag field. The second tag identifies a second memory address for a second block of main memory, and the first and second blocks are both mapped to the cache line. The method may further include storing a binary value in a last reference bit field to indicate whether the most recently received memory reference was directed to the current tag field or previous miss tag field.