AltMem DRAM Hybrid Memory Read Latency Reduction

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Solution Overview

Problem

Dynamic random-access memory (DRAM) devices experience long read latency times due to the need to close and open pages when a read command is directed at an address not on an open page, which can be exacerbated by the limitations of caches that are expensive and insufficient in capacity.

Innovation Solution

The use of alternative memory (AltMem) such as phase-change memory, spin-transfer torque random-access memory, or memristors in conjunction with DRAM, where data is stored in both memory types and the decision to read from DRAM or AltMem is made on a per-command basis, with the AltMem being used if DRAM read latency is greater, and the DRAM being 'primed' for subsequent commands to reduce overall latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a read command is directed at an address not on an open page, then the desired data can be accessed, but an existing open page must be closed first causing long read latency

Engineering Contradiction:
Improveread latencyVSAvoidpage switching time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent pre-opens multiple pages in the DRAM before they are actually needed, storing data from multiple pages simultaneously. When a read command arrives, the data can be immediately retrieved from the pre-opened page without closing other pages, thus eliminating page switching latency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an alternative memory (AltMem) as an intermediary layer between the DRAM and the processor. The AltMem stores copies of frequently accessed pages and can quickly provide data when DRAM page switching is required, acting as a buffer that reduces the impact of page closure operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If caches are used to reduce read latency, then access time improves, but the cost increases and capacity becomes insufficient

Engineering Contradiction:
Improveread latencyVSAvoidmemory capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent makes the DRAM banks multi-functional by allowing them to serve both as active working memory and as pre-fetch storage for future pages. The same DRAM infrastructure is used for both current operations and speculative pre-loading, eliminating the need for separate cache structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent creates copies of page data within the DRAM itself by pre-opening multiple pages and storing their contents simultaneously. These copies are made within the existing DRAM capacity rather than requiring external cache memory, effectively utilizing the DRAM's own resources for data replication.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS9916098B2Reducing read latency of memory modules
Publication Date: 2018.03.13 HEWLETT PACKARD ENTERPRISE DEV LP
  • US9916098B2 patent drawing
  • US9916098B2 patent drawing
  • US9916098B2 patent drawing

AI summary

Example implementations relate to using an alternative memory (AltMem) to reduce read latency of a memory module having a dynamic random-access memory (DRAM). In example implementations, write data may be written to the DRAM and to the AltMem. A read command may be issued to the AltMem if a DRAM read latency time for executing the read command is greater than an AltMem read latency time for executing the read command. Data read from the AltMem in response to the read command may be received.