Programmable ALU Delay Control for Throughput and Clock Gating
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Programmable circuits like FPGAs face challenges in increasing throughput and reducing power consumption due to the need to stop input data until calculation is complete and the difficulty in decreasing power consumption after calculation results are output, especially with a large number of ALUs.
Innovation Solution
An information processing apparatus with a programmable circuit featuring 2-input 1-output ALUs, a delay unit for independently setting data delays, and a controller for managing delay and calculation timing, allowing clock gating to be initiated only when final data is processed, enabling efficient data processing and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If configuration information is written to switch processing circuits, then the programmable circuit can implement different functions, but input data must be stopped until calculation is complete which decreases throughput
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing delay amounts for each ALU in advance before configuration switching occurs. When configuration information is written to switch processing circuits, the system immediately applies the pre-prepared delay amounts to maintain proper timing relationships, eliminating the need to stop input data and allowing continuous operation during function switching.
2Use of energy by stationary object
If power supply voltage is decreased to reduce power consumption, then power consumption decreases, but it is difficult to decrease power consumption for each ALU that has completed calculation before all results are output
Solution Approach 1:
The patent segments the power management approach by applying clock gating individually to each ALU based on its specific completion status. Instead of uniformly managing power for all ALUs, the system divides them into groups - those that have completed calculation and those that are still processing - and applies power reduction only to the completed ones, maintaining calculation efficiency while reducing overall power consumption.
Solution Approach 2:
The patent implements dynamic power management by continuously monitoring the completion status of each ALU and dynamically adjusting clock gating in real-time. When an ALU completes its calculation, the system immediately activates clock gating for that specific ALU, and deactivates it when the ALU needs to process new data, creating a dynamic response that optimizes power consumption without sacrificing productivity.
3Reliability
If input data is stopped to ensure data integrity during configuration switching, then data integrity is maintained, but throughput cannot be increased
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the appropriate delay amounts for each ALU before configuration switching occurs. This preparation allows the system to immediately apply correct timing adjustments when switching functions, maintaining data integrity through proper synchronization while avoiding the need to stop input data, thus preserving throughput.
Data Source
AI summary
The invention provides an apparatus comprising a programmable circuit including a plurality of 2-input 1-output ALUs, and an updating unit updating the programmable circuit according to circuit information, wherein each of the ALUs includes a calculation unit which performs a set type of calculation for two data and output a calculation result, a delay unit which delays the two input data in accordance with delay amounts independently set and supplies the delayed data to the calculation unit, and a controller which controls a delay amount for the delay unit and a calculation timing for the calculation unit in accordance with externally set information, wherein the updating unit sets clock gating start timings for a plurality of delay elements of the delay unit if an ALU of interest as a first processing circuit in the programmable circuit inputs final data to be processed.