Patterned Aluminum Grid Backside Conductor for Epitaxial Silicon Solar Cells
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Solution Overview
Problem
The high cost of conventional solar cells is driven by the expense of solar-grade silicon wafers and aluminum used for the backside electrode, which also contributes to environmental concerns related to fossil fuel usage.
Innovation Solution
A solar cell design utilizing a metallurgical-grade silicon substrate with a patterned aluminum backside electrode formed by screen-printing or aerosol-jet printing, reducing the need for extensive aluminum coverage and incorporating a heavily doped crystalline silicon layer as a back-surface-field to enhance efficiency and reduce material costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If aluminum paste is used to cover the whole backside of the solar cell, then sufficient passivation and electrical contact are ensured, but the cost of aluminum material increases significantly
Solution Approach 1:
The backside electrode is segmented into a grid pattern rather than being a continuous layer. The aluminum paste is applied only in specific finger and busbar regions, dividing the back surface into active electrode areas and inactive areas. This segmentation reduces the total amount of aluminum paste required while maintaining electrical contact functionality through the distributed grid structure.
Solution Approach 2:
Different regions of the backside are treated differently: the finger and busbar regions receive aluminum paste for electrical contact, while the inter-finger regions are left uncovered or receive different treatment for passivation. This local differentiation optimizes both electrical performance and material cost by applying aluminum only where electrically necessary.
2Reliability
If conventional solar-grade silicon wafers are used, then high purity and performance are achieved, but the manufacturing cost exceeds $100/kg
Solution Approach 1:
The invention employs metallurgical-grade silicon (MG-Si) substrate, which is a lower-cost alternative to conventional solar-grade silicon. The MG-Si substrate, while less pure, is sufficient for the thin-film solar cell structure when combined with epitaxial growth of high-quality silicon layers. This approach uses a cheaper base material that can be disposed of or recycled, replacing the expensive solar-grade silicon wafers.
3Reliability
If the backside is fully covered with aluminum paste, then complete passivation is achieved, but wafer-warping issues occur and material cost increases
Solution Approach 1:
The aluminum paste is applied in a segmented grid pattern rather than as a continuous layer. This segmentation creates thermal and mechanical stress distribution points that prevent uniform warping across the entire wafer surface. The gaps between aluminum fingers and busbars allow for stress relief and maintain wafer flatness during operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly lowers the manufacturing cost of solar cells while maintaining high energy-conversion efficiency (>17%) and addressing wafer-warping issues, enabling production at a price below $1/Wp.
Implementation Method 1
A solar cell converts light into electricity using the photoelectric effect
Implementation Method 2
Al forms a eutectic alloy with Si at a temperature of 577° C. During the firing process, a liquid Al—Si phase is formed according to the Al—Si phase diagram
Implementation Method 3
The molten Al—Si region acts as a sink for many impurities, giving a perfect gettering effect
Implementation Method 4
The p+ region generated by the firing of Al forms a back surface field (BSF), which introduce a barrier to minority carrier flow to the back surface of the solar cell
Data Source
AI summary
One embodiment of the present invention provides a solar cell. The solar cell includes a substrate, a first heavily doped crystalline-Si (c-Si) layer situated above the substrate, a lightly doped c-Si layer situated above the first heavily doped crystalline-Si layer, a second heavily doped c-Si layer situated above the lightly doped c-Si layer, a front side electrode grid situated above the second heavily doped c-Si layer, and a backside electrode grid situated on the backside of the substrate.